lk/linux-kernel-test
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

perf, x86: Make a second write to performance counter if needed

Browse Source 
On Netburst PMU we need a second write to a performance counter
due to cpu erratum.

A simple flag test instead of alternative instructions was choosen
because wrmsrl is already a macro and if virtualization is turned
on will need an additional wrapper call which is more expencise.

nb: we should propably switch to jump-labels as only this facility
reach the mainline.

Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Robert Richter <robert.richter@amd.com>
Cc: Lin Ming <ming.m.lin@intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
LKML-Reference: <20100602212304.GC5264@lenovo>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Cyrill Gorcunov
2010-06-03 01:23:04 +04:00
committed by Ingo Molnar
parent 8d2cacbbb8
commit 68aa00ac0a
2 changed files with 20 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
arch/x86/kernel/cpu/perf_event.c
View File

@@ -220,6 +220,7 @@ struct x86_pmu {
struct perf_event *event); struct perf_event *event);
struct event_constraint *event_constraints; struct event_constraint *event_constraints;
void (*quirks)(void); void (*quirks)(void);
int perfctr_second_write;
int (*cpu_prepare)(int cpu); int (*cpu_prepare)(int cpu);
void (*cpu_starting)(int cpu); void (*cpu_starting)(int cpu);
@@ -925,8 +926,17 @@ x86_perf_event_set_period(struct perf_event *event)
*/ */
atomic64_set(&hwc->prev_count, (u64)-left); atomic64_set(&hwc->prev_count, (u64)-left);
wrmsrl(hwc->event_base + idx, wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
/*
* Due to erratum on certan cpu we need
* a second write to be sure the register
* is updated properly
*/
if (x86_pmu.perfctr_second_write) {
wrmsrl(hwc->event_base + idx,
(u64)(-left) & x86_pmu.cntval_mask); (u64)(-left) & x86_pmu.cntval_mask);
}
perf_event_update_userpage(event); perf_event_update_userpage(event);

9
arch/x86/kernel/cpu/perf_event_p4.c
View File

@@ -829,6 +829,15 @@ static __initconst const struct x86_pmu p4_pmu = {
.max_period = (1ULL << 39) - 1, .max_period = (1ULL << 39) - 1,
.hw_config = p4_hw_config, .hw_config = p4_hw_config,
.schedule_events = p4_pmu_schedule_events, .schedule_events = p4_pmu_schedule_events,
/*
* This handles erratum N15 in intel doc 249199-029,
* the counter may not be updated correctly on write
* so we need a second write operation to do the trick
* (the official workaround didn't work)
*
* the former idea is taken from OProfile code
*/
.perfctr_second_write = 1,
}; };
static __init int p4_pmu_init(void) static __init int p4_pmu_init(void)