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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

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* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (549 commits)
  ALSA: hda - Fix ADC input-amp handling for Cx20549 codec
  ALSA: hda - Keep EAPD turned on for old Conexant chips
  ALSA: hda/realtek - Fix missing volume controls with ALC260
  ASoC: wm8940: Properly set codec->dapm.bias_level
  ALSA: hda - Fix pin-config for ASUS W90V
  ALSA: hda - Fix surround/CLFE headphone and speaker pins order
  ALSA: hda - Fix typo
  ALSA: Update the sound git tree URL
  ALSA: HDA: Add new revision for ALC662
  ASoC: max98095: Convert codec->hw_write to snd_soc_write
  ASoC: keep pointer to resource so it can be freed
  ASoC: sgtl5000: Fix wrong mask in some snd_soc_update_bits calls
  ASoC: wm8996: Fix wrong mask for setting WM8996_AIF_CLOCKING_2
  ASoC: da7210: Add support for line out and DAC
  ASoC: da7210: Add support for DAPM
  ALSA: hda/realtek - Fix DAC assignments of multiple speakers
  ASoC: Use SGTL5000_LINREG_VDDD_MASK instead of hardcoded mask value
  ASoC: Set sgtl5000->ldo in ldo_regulator_register
  ASoC: wm8996: Use SND_SOC_DAPM_AIF_OUT for AIF2 Capture
  ASoC: wm8994: Use SND_SOC_DAPM_AIF_OUT for AIF3 Capture
  ...
This commit is contained in:
Linus Torvalds
2011-10-28 14:25:01 -07:00
parent 0e59e7e7fe 8128c9f215
commit 68d99b2c8e
389 changed files with 25802 additions and 12244 deletions
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46
include/linux/mfd/twl6040.h
View File

@@ -68,11 +68,6 @@
#define TWL6040_REG_ACCCTL 0x2D
#define TWL6040_REG_STATUS 0x2E
#define TWL6040_CACHEREGNUM (TWL6040_REG_STATUS + 1)
#define TWL6040_VIOREGNUM 18
#define TWL6040_VDDREGNUM 21
/* INTID (0x03) fields */
#define TWL6040_THINT 0x01
@@ -125,34 +120,24 @@
#define TWL6040_LPLLFIN 0x08
#define TWL6040_HPLLSEL 0x10
/* HSLCTL (0x10) fields */
/* HSLCTL/R (0x10/0x11) fields */
#define TWL6040_HSDACMODEL 0x02
#define TWL6040_HSDRVMODEL 0x08
#define TWL6040_HSDACENA (1 << 0)
#define TWL6040_HSDACMODE (1 << 1)
#define TWL6040_HSDRVMODE (1 << 3)
/* HSRCTL (0x11) fields */
/* VIBCTLL/R (0x18/0x1A) fields */
#define TWL6040_HSDACMODER 0x02
#define TWL6040_HSDRVMODER 0x08
#define TWL6040_VIBENA (1 << 0)
#define TWL6040_VIBSEL (1 << 1)
#define TWL6040_VIBCTRL (1 << 2)
#define TWL6040_VIBCTRL_P (1 << 3)
#define TWL6040_VIBCTRL_N (1 << 4)
/* VIBCTLL (0x18) fields */
#define TWL6040_VIBENAL 0x01
#define TWL6040_VIBCTRLL 0x04
#define TWL6040_VIBCTRLLP 0x08
#define TWL6040_VIBCTRLLN 0x10
/* VIBDATL (0x19) fields */
/* VIBDATL/R (0x19/0x1B) fields */
#define TWL6040_VIBDAT_MAX 0x64
/* VIBCTLR (0x1A) fields */
#define TWL6040_VIBENAR 0x01
#define TWL6040_VIBCTRLR 0x04
#define TWL6040_VIBCTRLRP 0x08
#define TWL6040_VIBCTRLRN 0x10
/* GPOCTL (0x1E) fields */
#define TWL6040_GPO1 0x01
@@ -200,6 +185,7 @@ struct twl6040 {
int audpwron;
int power_count;
int rev;
u8 vibra_ctrl_cache[2];
int pll;
unsigned int sysclk;
@@ -224,5 +210,13 @@ int twl6040_get_pll(struct twl6040 *twl6040);
unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
int twl6040_irq_init(struct twl6040 *twl6040);
void twl6040_irq_exit(struct twl6040 *twl6040);
/* Get the combined status of the vibra control register */
int twl6040_get_vibralr_status(struct twl6040 *twl6040);
static inline int twl6040_get_revid(struct twl6040 *twl6040)
{
return twl6040->rev;
}
#endif /* End of __TWL6040_CODEC_H__ */

1
include/linux/mfd/wm8994/core.h
View File

@@ -20,6 +20,7 @@
enum wm8994_type {
WM8994 = 0,
WM8958 = 1,
WM1811 = 2,
};
struct regulator_dev;

88
include/linux/mfd/wm8994/registers.h
View File

@@ -72,6 +72,7 @@
#define WM8994_DC_SERVO_2 0x55
#define WM8994_DC_SERVO_4 0x57
#define WM8994_DC_SERVO_READBACK 0x58
#define WM8994_DC_SERVO_4E 0x59
#define WM8994_ANALOGUE_HP_1 0x60
#define WM8958_MIC_DETECT_1 0xD0
#define WM8958_MIC_DETECT_2 0xD1
@@ -133,6 +134,8 @@
#define WM8994_AIF1_DAC1_FILTERS_2 0x421
#define WM8994_AIF1_DAC2_FILTERS_1 0x422
#define WM8994_AIF1_DAC2_FILTERS_2 0x423
#define WM8958_AIF1_DAC1_NOISE_GATE 0x430
#define WM8958_AIF1_DAC2_NOISE_GATE 0x431
#define WM8994_AIF1_DRC1_1 0x440
#define WM8994_AIF1_DRC1_2 0x441
#define WM8994_AIF1_DRC1_3 0x442
@@ -190,6 +193,7 @@
#define WM8994_AIF2_ADC_FILTERS 0x510
#define WM8994_AIF2_DAC_FILTERS_1 0x520
#define WM8994_AIF2_DAC_FILTERS_2 0x521
#define WM8958_AIF2_DAC_NOISE_GATE 0x530
#define WM8994_AIF2_DRC_1 0x540
#define WM8994_AIF2_DRC_2 0x541
#define WM8994_AIF2_DRC_3 0x542
@@ -1920,6 +1924,44 @@
#define WM8994_LDO2_DISCH_SHIFT 0 /* LDO2_DISCH */
#define WM8994_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
/*
* R61 (0x3D) - MICBIAS1
*/
#define WM8958_MICB1_RATE 0x0020 /* MICB1_RATE */
#define WM8958_MICB1_RATE_MASK 0x0020 /* MICB1_RATE */
#define WM8958_MICB1_RATE_SHIFT 5 /* MICB1_RATE */
#define WM8958_MICB1_RATE_WIDTH 1 /* MICB1_RATE */
#define WM8958_MICB1_MODE 0x0010 /* MICB1_MODE */
#define WM8958_MICB1_MODE_MASK 0x0010 /* MICB1_MODE */
#define WM8958_MICB1_MODE_SHIFT 4 /* MICB1_MODE */
#define WM8958_MICB1_MODE_WIDTH 1 /* MICB1_MODE */
#define WM8958_MICB1_LVL_MASK 0x000E /* MICB1_LVL - [3:1] */
#define WM8958_MICB1_LVL_SHIFT 1 /* MICB1_LVL - [3:1] */
#define WM8958_MICB1_LVL_WIDTH 3 /* MICB1_LVL - [3:1] */
#define WM8958_MICB1_DISCH 0x0001 /* MICB1_DISCH */
#define WM8958_MICB1_DISCH_MASK 0x0001 /* MICB1_DISCH */
#define WM8958_MICB1_DISCH_SHIFT 0 /* MICB1_DISCH */
#define WM8958_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
/*
* R62 (0x3E) - MICBIAS2
*/
#define WM8958_MICB2_RATE 0x0020 /* MICB2_RATE */
#define WM8958_MICB2_RATE_MASK 0x0020 /* MICB2_RATE */
#define WM8958_MICB2_RATE_SHIFT 5 /* MICB2_RATE */
#define WM8958_MICB2_RATE_WIDTH 1 /* MICB2_RATE */
#define WM8958_MICB2_MODE 0x0010 /* MICB2_MODE */
#define WM8958_MICB2_MODE_MASK 0x0010 /* MICB2_MODE */
#define WM8958_MICB2_MODE_SHIFT 4 /* MICB2_MODE */
#define WM8958_MICB2_MODE_WIDTH 1 /* MICB2_MODE */
#define WM8958_MICB2_LVL_MASK 0x000E /* MICB2_LVL - [3:1] */
#define WM8958_MICB2_LVL_SHIFT 1 /* MICB2_LVL - [3:1] */
#define WM8958_MICB2_LVL_WIDTH 3 /* MICB2_LVL - [3:1] */
#define WM8958_MICB2_DISCH 0x0001 /* MICB2_DISCH */
#define WM8958_MICB2_DISCH_MASK 0x0001 /* MICB2_DISCH */
#define WM8958_MICB2_DISCH_SHIFT 0 /* MICB2_DISCH */
#define WM8958_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
/*
* R76 (0x4C) - Charge Pump (1)
*/
@@ -2027,6 +2069,10 @@
/*
* R96 (0x60) - Analogue HP (1)
*/
#define WM1811_HPOUT1_ATTN 0x0100 /* HPOUT1_ATTN */
#define WM1811_HPOUT1_ATTN_MASK 0x0100 /* HPOUT1_ATTN */
#define WM1811_HPOUT1_ATTN_SHIFT 8 /* HPOUT1_ATTN */
#define WM1811_HPOUT1_ATTN_WIDTH 1 /* HPOUT1_ATTN */
#define WM8994_HPOUT1L_RMV_SHORT 0x0080 /* HPOUT1L_RMV_SHORT */
#define WM8994_HPOUT1L_RMV_SHORT_MASK 0x0080 /* HPOUT1L_RMV_SHORT */
#define WM8994_HPOUT1L_RMV_SHORT_SHIFT 7 /* HPOUT1L_RMV_SHORT */
@@ -2948,6 +2994,34 @@
#define WM8994_AIF1DAC2_3D_ENA_SHIFT 8 /* AIF1DAC2_3D_ENA */
#define WM8994_AIF1DAC2_3D_ENA_WIDTH 1 /* AIF1DAC2_3D_ENA */
/*
* R1072 (0x430) - AIF1 DAC1 Noise Gate
*/
#define WM8958_AIF1DAC1_NG_HLD_MASK 0x0060 /* AIF1DAC1_NG_HLD - [6:5] */
#define WM8958_AIF1DAC1_NG_HLD_SHIFT 5 /* AIF1DAC1_NG_HLD - [6:5] */
#define WM8958_AIF1DAC1_NG_HLD_WIDTH 2 /* AIF1DAC1_NG_HLD - [6:5] */
#define WM8958_AIF1DAC1_NG_THR_MASK 0x000E /* AIF1DAC1_NG_THR - [3:1] */
#define WM8958_AIF1DAC1_NG_THR_SHIFT 1 /* AIF1DAC1_NG_THR - [3:1] */
#define WM8958_AIF1DAC1_NG_THR_WIDTH 3 /* AIF1DAC1_NG_THR - [3:1] */
#define WM8958_AIF1DAC1_NG_ENA 0x0001 /* AIF1DAC1_NG_ENA */
#define WM8958_AIF1DAC1_NG_ENA_MASK 0x0001 /* AIF1DAC1_NG_ENA */
#define WM8958_AIF1DAC1_NG_ENA_SHIFT 0 /* AIF1DAC1_NG_ENA */
#define WM8958_AIF1DAC1_NG_ENA_WIDTH 1 /* AIF1DAC1_NG_ENA */
/*
* R1073 (0x431) - AIF1 DAC2 Noise Gate
*/
#define WM8958_AIF1DAC2_NG_HLD_MASK 0x0060 /* AIF1DAC2_NG_HLD - [6:5] */
#define WM8958_AIF1DAC2_NG_HLD_SHIFT 5 /* AIF1DAC2_NG_HLD - [6:5] */
#define WM8958_AIF1DAC2_NG_HLD_WIDTH 2 /* AIF1DAC2_NG_HLD - [6:5] */
#define WM8958_AIF1DAC2_NG_THR_MASK 0x000E /* AIF1DAC2_NG_THR - [3:1] */
#define WM8958_AIF1DAC2_NG_THR_SHIFT 1 /* AIF1DAC2_NG_THR - [3:1] */
#define WM8958_AIF1DAC2_NG_THR_WIDTH 3 /* AIF1DAC2_NG_THR - [3:1] */
#define WM8958_AIF1DAC2_NG_ENA 0x0001 /* AIF1DAC2_NG_ENA */
#define WM8958_AIF1DAC2_NG_ENA_MASK 0x0001 /* AIF1DAC2_NG_ENA */
#define WM8958_AIF1DAC2_NG_ENA_SHIFT 0 /* AIF1DAC2_NG_ENA */
#define WM8958_AIF1DAC2_NG_ENA_WIDTH 1 /* AIF1DAC2_NG_ENA */
/*
* R1088 (0x440) - AIF1 DRC1 (1)
*/
@@ -3559,6 +3633,20 @@
#define WM8994_AIF2DAC_3D_ENA_SHIFT 8 /* AIF2DAC_3D_ENA */
#define WM8994_AIF2DAC_3D_ENA_WIDTH 1 /* AIF2DAC_3D_ENA */
/*
* R1328 (0x530) - AIF2 DAC Noise Gate
*/
#define WM8958_AIF2DAC_NG_HLD_MASK 0x0060 /* AIF2DAC_NG_HLD - [6:5] */
#define WM8958_AIF2DAC_NG_HLD_SHIFT 5 /* AIF2DAC_NG_HLD - [6:5] */
#define WM8958_AIF2DAC_NG_HLD_WIDTH 2 /* AIF2DAC_NG_HLD - [6:5] */
#define WM8958_AIF2DAC_NG_THR_MASK 0x000E /* AIF2DAC_NG_THR - [3:1] */
#define WM8958_AIF2DAC_NG_THR_SHIFT 1 /* AIF2DAC_NG_THR - [3:1] */
#define WM8958_AIF2DAC_NG_THR_WIDTH 3 /* AIF2DAC_NG_THR - [3:1] */
#define WM8958_AIF2DAC_NG_ENA 0x0001 /* AIF2DAC_NG_ENA */
#define WM8958_AIF2DAC_NG_ENA_MASK 0x0001 /* AIF2DAC_NG_ENA */
#define WM8958_AIF2DAC_NG_ENA_SHIFT 0 /* AIF2DAC_NG_ENA */
#define WM8958_AIF2DAC_NG_ENA_WIDTH 1 /* AIF2DAC_NG_ENA */
/*
* R1344 (0x540) - AIF2 DRC (1)
*/