Merge commit 'gcl/next' into next
This commit is contained in:
Benjamin Herrenschmidt
@@ -17,6 +17,7 @@
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compatible = "schindler,cm5200";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&mpc5200_pic>;
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||||
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||||
cpus {
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||||
#address-cells = <1>;
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@@ -66,7 +67,6 @@
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x600 0x10>;
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interrupts = <1 9 0>;
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interrupt-parent = <&mpc5200_pic>;
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fsl,has-wdt;
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};
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@@ -74,84 +74,76 @@
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x610 0x10>;
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interrupts = <1 10 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@620 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x620 0x10>;
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interrupts = <1 11 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@630 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x630 0x10>;
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interrupts = <1 12 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@640 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x640 0x10>;
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interrupts = <1 13 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@650 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x650 0x10>;
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interrupts = <1 14 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@660 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x660 0x10>;
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interrupts = <1 15 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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timer@670 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
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reg = <0x670 0x10>;
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interrupts = <1 16 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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rtc@800 { // Real time clock
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compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
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reg = <0x800 0x100>;
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interrupts = <1 5 0 1 6 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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gpio@b00 {
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gpio_simple: gpio@b00 {
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compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
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reg = <0xb00 0x40>;
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interrupts = <1 7 0>;
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interrupt-parent = <&mpc5200_pic>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio@c00 {
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gpio_wkup: gpio@c00 {
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compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
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reg = <0xc00 0x40>;
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interrupts = <1 8 0 0 3 0>;
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interrupt-parent = <&mpc5200_pic>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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spi@f00 {
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compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
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reg = <0xf00 0x20>;
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interrupts = <2 13 0 2 14 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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usb@1000 {
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compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
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reg = <0x1000 0xff>;
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interrupts = <2 6 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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dma-controller@1200 {
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@@ -161,7 +153,6 @@
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3 4 0 3 5 0 3 6 0 3 7 0
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||||
3 8 0 3 9 0 3 10 0 3 11 0
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||||
3 12 0 3 13 0 3 14 0 3 15 0>;
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interrupt-parent = <&mpc5200_pic>;
|
||||
};
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||||
|
||||
xlb@1f00 {
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||||
@@ -170,48 +161,34 @@
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};
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||||
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serial@2000 { // PSC1
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device_type = "serial";
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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port-number = <0>; // Logical port assignment
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reg = <0x2000 0x100>;
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interrupts = <2 1 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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serial@2200 { // PSC2
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device_type = "serial";
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compatible = "fsl,mpc5200-psc-uart";
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port-number = <1>; // Logical port assignment
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2200 0x100>;
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interrupts = <2 2 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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serial@2400 { // PSC3
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device_type = "serial";
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compatible = "fsl,mpc5200-psc-uart";
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port-number = <2>; // Logical port assignment
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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reg = <0x2400 0x100>;
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interrupts = <2 3 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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serial@2c00 { // PSC6
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device_type = "serial";
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
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port-number = <5>; // Logical port assignment
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reg = <0x2c00 0x100>;
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interrupts = <2 4 0>;
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interrupt-parent = <&mpc5200_pic>;
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};
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ethernet@3000 {
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device_type = "network";
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compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
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reg = <0x3000 0x400>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <2 5 0>;
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interrupt-parent = <&mpc5200_pic>;
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phy-handle = <&phy0>;
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};
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@@ -221,10 +198,8 @@
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compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
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reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
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interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
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interrupt-parent = <&mpc5200_pic>;
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phy0: ethernet-phy@0 {
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device_type = "ethernet-phy";
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reg = <0>;
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};
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};
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@@ -235,7 +210,6 @@
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compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
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reg = <0x3d40 0x40>;
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interrupts = <2 16 0>;
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interrupt-parent = <&mpc5200_pic>;
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fsl5200-clocking;
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};
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@@ -245,9 +219,8 @@
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};
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};
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lpb {
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model = "fsl,lpb";
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compatible = "fsl,lpb";
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localbus {
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compatible = "fsl,mpc5200b-lpb","simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0xfc000000 0x2000000>;
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254
arch/powerpc/boot/dts/digsy_mtc.dts
Normal file
254
arch/powerpc/boot/dts/digsy_mtc.dts
Normal file
@@ -0,0 +1,254 @@
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/*
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* Digsy MTC board Device Tree Source
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||||
*
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||||
* Copyright (C) 2009 Semihalf
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*
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* Based on the CM5200 by M. Balakowicz
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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||||
* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "intercontrol,digsy-mtc";
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compatible = "intercontrol,digsy-mtc";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&mpc5200_pic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,5200@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <0x4000>; // L1, 16K
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i-cache-size = <0x4000>; // L1, 16K
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timebase-frequency = <0>; // from bootloader
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bus-frequency = <0>; // from bootloader
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clock-frequency = <0>; // from bootloader
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x02000000>; // 32MB
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};
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soc5200@f0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc5200b-immr";
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ranges = <0 0xf0000000 0x0000c000>;
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reg = <0xf0000000 0x00000100>;
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bus-frequency = <0>; // from bootloader
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system-frequency = <0>; // from bootloader
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cdm@200 {
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compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
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reg = <0x200 0x38>;
|
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};
|
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mpc5200_pic: interrupt-controller@500 {
|
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// 5200 interrupts are encoded into two levels;
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||||
interrupt-controller;
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||||
#interrupt-cells = <3>;
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compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
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reg = <0x500 0x80>;
|
||||
};
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|
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timer@600 { // General Purpose Timer
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compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <1 9 0>;
|
||||
fsl,has-wdt;
|
||||
};
|
||||
|
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timer@610 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x610 0x10>;
|
||||
interrupts = <1 10 0>;
|
||||
};
|
||||
|
||||
timer@620 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x620 0x10>;
|
||||
interrupts = <1 11 0>;
|
||||
};
|
||||
|
||||
timer@630 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x630 0x10>;
|
||||
interrupts = <1 12 0>;
|
||||
};
|
||||
|
||||
timer@640 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x640 0x10>;
|
||||
interrupts = <1 13 0>;
|
||||
};
|
||||
|
||||
timer@650 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x650 0x10>;
|
||||
interrupts = <1 14 0>;
|
||||
};
|
||||
|
||||
timer@660 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x660 0x10>;
|
||||
interrupts = <1 15 0>;
|
||||
};
|
||||
|
||||
timer@670 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x670 0x10>;
|
||||
interrupts = <1 16 0>;
|
||||
};
|
||||
|
||||
gpio_simple: gpio@b00 {
|
||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <1 7 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio_wkup: gpio@c00 {
|
||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||
reg = <0xc00 0x40>;
|
||||
interrupts = <1 8 0 0 3 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||
reg = <0xf00 0x20>;
|
||||
interrupts = <2 13 0 2 14 0>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <0x1000 0xff>;
|
||||
interrupts = <2 6 0>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||
reg = <0x1200 0x80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 10 0 3 11 0
|
||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
|
||||
reg = <0x1f00 0x100>;
|
||||
};
|
||||
|
||||
serial@2400 { // PSC3
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
reg = <0x2400 0x100>;
|
||||
interrupts = <2 3 0>;
|
||||
};
|
||||
|
||||
serial@2600 { // PSC4
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
reg = <0x2600 0x100>;
|
||||
interrupts = <2 11 0>;
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
mdio@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <2 7 0>;
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <0x3d00 0x40>;
|
||||
interrupts = <2 15 0>;
|
||||
fsl5200-clocking;
|
||||
|
||||
rtc@50 {
|
||||
compatible = "at,24c08";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1339";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
lpb {
|
||||
compatible = "fsl,mpc5200b-lpb","simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0xff000000 0x1000000>;
|
||||
|
||||
// 16-bit flash device at LocalPlus Bus CS0
|
||||
flash@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <2>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "kernel";
|
||||
reg = <0x0 0x00200000>;
|
||||
};
|
||||
partition@200000 {
|
||||
label = "root";
|
||||
reg = <0x00200000 0x00300000>;
|
||||
};
|
||||
partition@500000 {
|
||||
label = "user";
|
||||
reg = <0x00500000 0x00a00000>;
|
||||
};
|
||||
partition@f00000 {
|
||||
label = "u-boot";
|
||||
reg = <0x00f00000 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -17,6 +17,7 @@
|
||||
compatible = "fsl,lite5200";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
@@ -58,96 +59,74 @@
|
||||
// 5200 interrupts are encoded into two levels;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
device_type = "interrupt-controller";
|
||||
compatible = "fsl,mpc5200-pic";
|
||||
reg = <0x500 0x80>;
|
||||
};
|
||||
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <0>;
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <1 9 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
timer@610 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <1>;
|
||||
reg = <0x610 0x10>;
|
||||
interrupts = <1 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@620 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <2>;
|
||||
reg = <0x620 0x10>;
|
||||
interrupts = <1 11 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@630 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <3>;
|
||||
reg = <0x630 0x10>;
|
||||
interrupts = <1 12 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@640 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <4>;
|
||||
reg = <0x640 0x10>;
|
||||
interrupts = <1 13 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@650 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <5>;
|
||||
reg = <0x650 0x10>;
|
||||
interrupts = <1 14 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@660 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <6>;
|
||||
reg = <0x660 0x10>;
|
||||
interrupts = <1 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@670 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
cell-index = <7>;
|
||||
reg = <0x670 0x10>;
|
||||
interrupts = <1 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
rtc@800 { // Real time clock
|
||||
compatible = "fsl,mpc5200-rtc";
|
||||
reg = <0x800 0x100>;
|
||||
interrupts = <1 5 0 1 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
can@900 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
cell-index = <0>;
|
||||
interrupts = <2 17 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <0x900 0x80>;
|
||||
};
|
||||
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
cell-index = <1>;
|
||||
interrupts = <2 18 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <0x980 0x80>;
|
||||
};
|
||||
|
||||
@@ -155,39 +134,33 @@
|
||||
compatible = "fsl,mpc5200-gpio";
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <1 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
gpio@c00 {
|
||||
compatible = "fsl,mpc5200-gpio-wkup";
|
||||
reg = <0xc00 0x40>;
|
||||
interrupts = <1 8 0 0 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
compatible = "fsl,mpc5200-spi";
|
||||
reg = <0xf00 0x20>;
|
||||
interrupts = <2 13 0 2 14 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <0x1000 0xff>;
|
||||
interrupts = <2 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
device_type = "dma-controller";
|
||||
compatible = "fsl,mpc5200-bestcomm";
|
||||
reg = <0x1200 0x80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 10 0 3 11 0
|
||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
@@ -196,13 +169,10 @@
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <0>; // Logical port assignment
|
||||
cell-index = <0>;
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <2 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
// PSC2 in ac97 mode example
|
||||
@@ -211,7 +181,6 @@
|
||||
// cell-index = <1>;
|
||||
// reg = <0x2200 0x100>;
|
||||
// interrupts = <2 2 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
// PSC3 in CODEC mode example
|
||||
@@ -220,27 +189,22 @@
|
||||
// cell-index = <2>;
|
||||
// reg = <0x2400 0x100>;
|
||||
// interrupts = <2 3 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
// PSC4 in uart mode example
|
||||
//serial@2600 { // PSC4
|
||||
// device_type = "serial";
|
||||
// compatible = "fsl,mpc5200-psc-uart";
|
||||
// cell-index = <3>;
|
||||
// reg = <0x2600 0x100>;
|
||||
// interrupts = <2 11 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
// PSC5 in uart mode example
|
||||
//serial@2800 { // PSC5
|
||||
// device_type = "serial";
|
||||
// compatible = "fsl,mpc5200-psc-uart";
|
||||
// cell-index = <4>;
|
||||
// reg = <0x2800 0x100>;
|
||||
// interrupts = <2 12 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
// PSC6 in spi mode example
|
||||
@@ -249,16 +213,13 @@
|
||||
// cell-index = <5>;
|
||||
// reg = <0x2c00 0x100>;
|
||||
// interrupts = <2 4 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5200-fec";
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
@@ -268,30 +229,24 @@
|
||||
compatible = "fsl,mpc5200-mdio";
|
||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
device_type = "ata";
|
||||
compatible = "fsl,mpc5200-ata";
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <2 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <0>;
|
||||
reg = <0x3d00 0x40>;
|
||||
interrupts = <2 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
||||
@@ -299,14 +254,12 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <1>;
|
||||
reg = <0x3d40 0x40>;
|
||||
interrupts = <2 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200-sram","sram";
|
||||
compatible = "fsl,mpc5200-sram";
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
};
|
||||
@@ -325,7 +278,6 @@
|
||||
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||
|
||||
@@ -17,6 +17,7 @@
|
||||
compatible = "fsl,lite5200b";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
@@ -58,136 +59,112 @@
|
||||
// 5200 interrupts are encoded into two levels;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
device_type = "interrupt-controller";
|
||||
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||
reg = <0x500 0x80>;
|
||||
};
|
||||
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <0>;
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <1 9 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
timer@610 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <1>;
|
||||
reg = <0x610 0x10>;
|
||||
interrupts = <1 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@620 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <2>;
|
||||
reg = <0x620 0x10>;
|
||||
interrupts = <1 11 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@630 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <3>;
|
||||
reg = <0x630 0x10>;
|
||||
interrupts = <1 12 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@640 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <4>;
|
||||
reg = <0x640 0x10>;
|
||||
interrupts = <1 13 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@650 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <5>;
|
||||
reg = <0x650 0x10>;
|
||||
interrupts = <1 14 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@660 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <6>;
|
||||
reg = <0x660 0x10>;
|
||||
interrupts = <1 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@670 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <7>;
|
||||
reg = <0x670 0x10>;
|
||||
interrupts = <1 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
rtc@800 { // Real time clock
|
||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||
reg = <0x800 0x100>;
|
||||
interrupts = <1 5 0 1 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
can@900 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
cell-index = <0>;
|
||||
interrupts = <2 17 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <0x900 0x80>;
|
||||
};
|
||||
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
cell-index = <1>;
|
||||
interrupts = <2 18 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <0x980 0x80>;
|
||||
};
|
||||
|
||||
gpio@b00 {
|
||||
gpio_simple: gpio@b00 {
|
||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <1 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio@c00 {
|
||||
gpio_wkup: gpio@c00 {
|
||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||
reg = <0xc00 0x40>;
|
||||
interrupts = <1 8 0 0 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||
reg = <0xf00 0x20>;
|
||||
interrupts = <2 13 0 2 14 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <0x1000 0xff>;
|
||||
interrupts = <2 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
device_type = "dma-controller";
|
||||
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||
reg = <0x1200 0x80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 10 0 3 11 0
|
||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
@@ -196,13 +173,10 @@
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <0>; // Logical port assignment
|
||||
cell-index = <0>;
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <2 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
// PSC2 in ac97 mode example
|
||||
@@ -211,7 +185,6 @@
|
||||
// cell-index = <1>;
|
||||
// reg = <0x2200 0x100>;
|
||||
// interrupts = <2 2 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
// PSC3 in CODEC mode example
|
||||
@@ -220,27 +193,22 @@
|
||||
// cell-index = <2>;
|
||||
// reg = <0x2400 0x100>;
|
||||
// interrupts = <2 3 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
// PSC4 in uart mode example
|
||||
//serial@2600 { // PSC4
|
||||
// device_type = "serial";
|
||||
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
// cell-index = <3>;
|
||||
// reg = <0x2600 0x100>;
|
||||
// interrupts = <2 11 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
// PSC5 in uart mode example
|
||||
//serial@2800 { // PSC5
|
||||
// device_type = "serial";
|
||||
// compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
// cell-index = <4>;
|
||||
// reg = <0x2800 0x100>;
|
||||
// interrupts = <2 12 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
// PSC6 in spi mode example
|
||||
@@ -249,49 +217,40 @@
|
||||
// cell-index = <5>;
|
||||
// reg = <0x2c00 0x100>;
|
||||
// interrupts = <2 4 0>;
|
||||
// interrupt-parent = <&mpc5200_pic>;
|
||||
//};
|
||||
|
||||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
mdio@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
|
||||
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
device_type = "ata";
|
||||
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <2 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <0>;
|
||||
reg = <0x3d00 0x40>;
|
||||
interrupts = <2 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
||||
@@ -299,14 +258,13 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <1>;
|
||||
reg = <0x3d40 0x40>;
|
||||
interrupts = <2 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
};
|
||||
@@ -330,7 +288,6 @@
|
||||
0xc800 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||
|
||||
318
arch/powerpc/boot/dts/media5200.dts
Normal file
318
arch/powerpc/boot/dts/media5200.dts
Normal file
@@ -0,0 +1,318 @@
|
||||
/*
|
||||
* Freescale Media5200 board Device Tree Source
|
||||
*
|
||||
* Copyright 2009 Secret Lab Technologies Ltd.
|
||||
* Grant Likely <grant.likely@secretlab.ca>
|
||||
* Steven Cavanagh <scavanagh@secretlab.ca>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "fsl,media5200";
|
||||
compatible = "fsl,media5200";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
aliases {
|
||||
console = &console;
|
||||
ethernet0 = ð0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
linux,stdout-path = &console;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,5200@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <0x4000>; // L1, 16K
|
||||
i-cache-size = <0x4000>; // L1, 16K
|
||||
timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
|
||||
bus-frequency = <132000000>; // 132 MHz
|
||||
clock-frequency = <396000000>; // 396 MHz
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x08000000>; // 128MB RAM
|
||||
};
|
||||
|
||||
soc@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200b-immr";
|
||||
ranges = <0 0xf0000000 0x0000c000>;
|
||||
reg = <0xf0000000 0x00000100>;
|
||||
bus-frequency = <132000000>;// 132 MHz
|
||||
system-frequency = <0>; // from bootloader
|
||||
|
||||
cdm@200 {
|
||||
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
|
||||
reg = <0x200 0x38>;
|
||||
};
|
||||
|
||||
mpc5200_pic: interrupt-controller@500 {
|
||||
// 5200 interrupts are encoded into two levels;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||
reg = <0x500 0x80>;
|
||||
};
|
||||
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <1 9 0>;
|
||||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
timer@610 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x610 0x10>;
|
||||
interrupts = <1 10 0>;
|
||||
};
|
||||
|
||||
timer@620 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x620 0x10>;
|
||||
interrupts = <1 11 0>;
|
||||
};
|
||||
|
||||
timer@630 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x630 0x10>;
|
||||
interrupts = <1 12 0>;
|
||||
};
|
||||
|
||||
timer@640 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x640 0x10>;
|
||||
interrupts = <1 13 0>;
|
||||
};
|
||||
|
||||
timer@650 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x650 0x10>;
|
||||
interrupts = <1 14 0>;
|
||||
};
|
||||
|
||||
timer@660 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x660 0x10>;
|
||||
interrupts = <1 15 0>;
|
||||
};
|
||||
|
||||
timer@670 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x670 0x10>;
|
||||
interrupts = <1 16 0>;
|
||||
};
|
||||
|
||||
rtc@800 { // Real time clock
|
||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||
reg = <0x800 0x100>;
|
||||
interrupts = <1 5 0 1 6 0>;
|
||||
};
|
||||
|
||||
can@900 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
interrupts = <2 17 0>;
|
||||
reg = <0x900 0x80>;
|
||||
};
|
||||
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
interrupts = <2 18 0>;
|
||||
reg = <0x980 0x80>;
|
||||
};
|
||||
|
||||
gpio_simple: gpio@b00 {
|
||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <1 7 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio_wkup: gpio@c00 {
|
||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||
reg = <0xc00 0x40>;
|
||||
interrupts = <1 8 0 0 3 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||
reg = <0xf00 0x20>;
|
||||
interrupts = <2 13 0 2 14 0>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <0x1000 0x100>;
|
||||
interrupts = <2 6 0>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||
reg = <0x1200 0x80>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 10 0 3 11 0
|
||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
|
||||
reg = <0x1f00 0x100>;
|
||||
};
|
||||
|
||||
// PSC6 in uart mode
|
||||
console: serial@2c00 { // PSC6
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
cell-index = <5>;
|
||||
port-number = <0>; // Logical port assignment
|
||||
reg = <0x2c00 0x100>;
|
||||
interrupts = <2 4 0>;
|
||||
};
|
||||
|
||||
eth0: ethernet@3000 {
|
||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
mdio@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <2 7 0>;
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <0x3d00 0x40>;
|
||||
interrupts = <2 15 0>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
||||
i2c@3d40 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <0x3d40 0x40>;
|
||||
interrupts = <2 16 0>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci@f0000d00 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
|
||||
reg = <0xf0000d00 0x100>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
|
||||
0xc000 0 0 2 &media5200_fpga 0 3
|
||||
0xc000 0 0 3 &media5200_fpga 0 4
|
||||
0xc000 0 0 4 &media5200_fpga 0 5
|
||||
|
||||
0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
|
||||
0xc800 0 0 2 &media5200_fpga 0 4
|
||||
0xc800 0 0 3 &media5200_fpga 0 5
|
||||
0xc800 0 0 4 &media5200_fpga 0 2
|
||||
|
||||
0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
|
||||
0xd000 0 0 2 &media5200_fpga 0 5
|
||||
|
||||
0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
|
||||
>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
|
||||
};
|
||||
|
||||
localbus {
|
||||
compatible = "fsl,mpc5200b-lpb","simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
|
||||
ranges = < 0 0 0xfc000000 0x02000000
|
||||
1 0 0xfe000000 0x02000000
|
||||
2 0 0xf0010000 0x00010000
|
||||
3 0 0xf0020000 0x00010000 >;
|
||||
|
||||
flash@0,0 {
|
||||
compatible = "amd,am29lv28ml", "cfi-flash";
|
||||
reg = <0 0x0 0x2000000>; // 32 MB
|
||||
bank-width = <4>; // Width in bytes of the flash bank
|
||||
device-width = <2>; // Two devices on each bank
|
||||
};
|
||||
|
||||
flash@1,0 {
|
||||
compatible = "amd,am29lv28ml", "cfi-flash";
|
||||
reg = <1 0 0x2000000>; // 32 MB
|
||||
bank-width = <4>; // Width in bytes of the flash bank
|
||||
device-width = <2>; // Two devices on each bank
|
||||
};
|
||||
|
||||
media5200_fpga: fpga@2,0 {
|
||||
compatible = "fsl,media5200-fpga";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>; // 0:bank 1:id; no type field
|
||||
reg = <2 0 0x10000>;
|
||||
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <0 0 3 // IRQ bank 0
|
||||
1 1 3>; // IRQ bank 1
|
||||
};
|
||||
|
||||
uart@3,0 {
|
||||
compatible = "ti,tl16c752bpt";
|
||||
reg = <3 0 0x10000>;
|
||||
interrupt-parent = <&media5200_fpga>;
|
||||
interrupts = <0 0 0 1>; // 2 irqs
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -17,6 +17,7 @@
|
||||
compatible = "promess,motionpro";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
@@ -66,7 +67,6 @@
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <1 9 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
@@ -74,35 +74,30 @@
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x610 0x10>;
|
||||
interrupts = <1 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@620 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x620 0x10>;
|
||||
interrupts = <1 11 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@630 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x630 0x10>;
|
||||
interrupts = <1 12 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@640 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x640 0x10>;
|
||||
interrupts = <1 13 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
timer@650 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
reg = <0x650 0x10>;
|
||||
interrupts = <1 14 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
motionpro-led@660 { // Motion-PRO status LED
|
||||
@@ -110,7 +105,6 @@
|
||||
label = "motionpro-statusled";
|
||||
reg = <0x660 0x10>;
|
||||
interrupts = <1 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
blink-delay = <100>; // 100 msec
|
||||
};
|
||||
|
||||
@@ -119,49 +113,46 @@
|
||||
label = "motionpro-readyled";
|
||||
reg = <0x670 0x10>;
|
||||
interrupts = <1 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
rtc@800 { // Real time clock
|
||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||
reg = <0x800 0x100>;
|
||||
interrupts = <1 5 0 1 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
interrupts = <2 18 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <0x980 0x80>;
|
||||
};
|
||||
|
||||
gpio@b00 {
|
||||
gpio_simple: gpio@b00 {
|
||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <1 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio@c00 {
|
||||
gpio_wkup: gpio@c00 {
|
||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||
reg = <0xc00 0x40>;
|
||||
interrupts = <1 8 0 0 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
spi@f00 {
|
||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||
reg = <0xf00 0x20>;
|
||||
interrupts = <2 13 0 2 14 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <0x1000 0xff>;
|
||||
interrupts = <2 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
@@ -171,7 +162,6 @@
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 10 0 3 11 0
|
||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
@@ -180,12 +170,9 @@
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <0>; // Logical port assignment
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <2 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
// PSC2 in spi master mode
|
||||
@@ -194,26 +181,20 @@
|
||||
cell-index = <1>;
|
||||
reg = <0x2200 0x100>;
|
||||
interrupts = <2 2 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
// PSC5 in uart mode
|
||||
serial@2800 { // PSC5
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <4>; // Logical port assignment
|
||||
reg = <0x2800 0x100>;
|
||||
interrupts = <2 12 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
@@ -223,10 +204,8 @@
|
||||
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
phy0: ethernet-phy@2 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <2>;
|
||||
};
|
||||
};
|
||||
@@ -235,7 +214,6 @@
|
||||
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <2 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
i2c@3d40 {
|
||||
@@ -244,7 +222,6 @@
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <0x3d40 0x40>;
|
||||
interrupts = <2 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
|
||||
rtc@68 {
|
||||
@@ -259,8 +236,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
lpb {
|
||||
compatible = "fsl,lpb";
|
||||
localbus {
|
||||
compatible = "fsl,mpc5200b-lpb","simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0xff000000 0x01000000
|
||||
@@ -273,7 +250,6 @@
|
||||
compatible = "promess,motionpro-kollmorgen";
|
||||
reg = <1 0 0x10000>;
|
||||
interrupts = <1 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
// 8-bit board CPLD on LocalPlus Bus CS2
|
||||
|
||||
@@ -19,6 +19,7 @@
|
||||
compatible = "phytec,pcm030";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
@@ -29,26 +30,26 @@
|
||||
reg = <0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <0x4000>; /* L1, 16K */
|
||||
i-cache-size = <0x4000>; /* L1, 16K */
|
||||
timebase-frequency = <0>; /* From Bootloader */
|
||||
bus-frequency = <0>; /* From Bootloader */
|
||||
clock-frequency = <0>; /* From Bootloader */
|
||||
d-cache-size = <0x4000>; // L1, 16K
|
||||
i-cache-size = <0x4000>; // L1, 16K
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x04000000>; /* 64MB */
|
||||
reg = <0x00000000 0x04000000>; // 64MB
|
||||
};
|
||||
|
||||
soc5200@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc5200b-immr";
|
||||
ranges = <0x0 0xf0000000 0x0000c000>;
|
||||
bus-frequency = <0>; /* From bootloader */
|
||||
system-frequency = <0>; /* From bootloader */
|
||||
ranges = <0 0xf0000000 0x0000c000>;
|
||||
bus-frequency = <0>; // from bootloader
|
||||
system-frequency = <0>; // from bootloader
|
||||
|
||||
cdm@200 {
|
||||
compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
|
||||
@@ -56,87 +57,70 @@
|
||||
};
|
||||
|
||||
mpc5200_pic: interrupt-controller@500 {
|
||||
/* 5200 interrupts are encoded into two levels; */
|
||||
// 5200 interrupts are encoded into two levels;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
device_type = "interrupt-controller";
|
||||
compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
|
||||
reg = <0x500 0x80>;
|
||||
};
|
||||
|
||||
timer@600 { /* General Purpose Timer */
|
||||
timer@600 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <0>;
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <0x1 0x9 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <1 9 0>;
|
||||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
timer@610 { /* General Purpose Timer */
|
||||
timer@610 { // General Purpose Timer
|
||||
compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
|
||||
cell-index = <1>;
|
||||
reg = <0x610 0x10>;
|
||||
interrupts = <0x1 0xa 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <1 10 0>;
|
||||
};
|
||||
|
||||
gpt2: timer@620 { /* General Purpose Timer in GPIO mode */
|
||||
gpt2: timer@620 { // General Purpose Timer in GPIO mode
|
||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||
cell-index = <2>;
|
||||
reg = <0x620 0x10>;
|
||||
interrupts = <0x1 0xb 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <1 11 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
|
||||
gpt3: timer@630 { // General Purpose Timer in GPIO mode
|
||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||
cell-index = <3>;
|
||||
reg = <0x630 0x10>;
|
||||
interrupts = <0x1 0xc 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <1 12 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
|
||||
gpt4: timer@640 { // General Purpose Timer in GPIO mode
|
||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||
cell-index = <4>;
|
||||
reg = <0x640 0x10>;
|
||||
interrupts = <0x1 0xd 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <1 13 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
|
||||
gpt5: timer@650 { // General Purpose Timer in GPIO mode
|
||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||
cell-index = <5>;
|
||||
reg = <0x650 0x10>;
|
||||
interrupts = <0x1 0xe 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <1 14 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpt6: timer@660 { /* General Purpose Timer in GPIO mode */
|
||||
gpt6: timer@660 { // General Purpose Timer in GPIO mode
|
||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||
cell-index = <6>;
|
||||
reg = <0x660 0x10>;
|
||||
interrupts = <0x1 0xf 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <1 15 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpt7: timer@670 { /* General Purpose Timer in GPIO mode */
|
||||
gpt7: timer@670 { // General Purpose Timer in GPIO mode
|
||||
compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
|
||||
cell-index = <7>;
|
||||
reg = <0x670 0x10>;
|
||||
interrupts = <0x1 0x10 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <1 16 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
@@ -144,40 +128,33 @@
|
||||
rtc@800 { // Real time clock
|
||||
compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
|
||||
reg = <0x800 0x100>;
|
||||
interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <1 5 0 1 6 0>;
|
||||
};
|
||||
|
||||
can@900 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
cell-index = <0>;
|
||||
interrupts = <0x2 0x11 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <2 17 0>;
|
||||
reg = <0x900 0x80>;
|
||||
};
|
||||
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
|
||||
cell-index = <1>;
|
||||
interrupts = <0x2 0x12 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <2 18 0>;
|
||||
reg = <0x980 0x80>;
|
||||
};
|
||||
|
||||
gpio_simple: gpio@b00 {
|
||||
compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <0x1 0x7 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <1 7 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
gpio_wkup: gpio-wkup@c00 {
|
||||
gpio_wkup: gpio@c00 {
|
||||
compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
|
||||
reg = <0xc00 0x40>;
|
||||
interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <1 8 0 0 3 0>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
@@ -185,26 +162,22 @@
|
||||
spi@f00 {
|
||||
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
|
||||
reg = <0xf00 0x20>;
|
||||
interrupts = <0x2 0xd 0x0 0x2 0xe 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <2 13 0 2 14 0>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <0x1000 0xff>;
|
||||
interrupts = <0x2 0x6 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <2 6 0>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
device_type = "dma-controller";
|
||||
compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
|
||||
reg = <0x1200 0x80>;
|
||||
interrupts = <0x3 0x0 0x0 0x3 0x1 0x0 0x3 0x2 0x0 0x3 0x3 0x0
|
||||
0x3 0x4 0x0 0x3 0x5 0x0 0x3 0x6 0x0 0x3 0x7 0x0
|
||||
0x3 0x8 0x0 0x3 0x9 0x0 0x3 0xa 0x0 0x3 0xb 0x0
|
||||
0x3 0xc 0x0 0x3 0xd 0x0 0x3 0xe 0x0 0x3 0xf 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 10 0 3 11 0
|
||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
@@ -213,24 +186,19 @@
|
||||
};
|
||||
|
||||
ac97@2000 { /* PSC1 in ac97 mode */
|
||||
device_type = "sound";
|
||||
compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97";
|
||||
cell-index = <0>;
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <0x2 0x2 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <2 1 0>;
|
||||
};
|
||||
|
||||
/* PSC2 port is used by CAN1/2 */
|
||||
|
||||
serial@2400 { /* PSC3 in UART mode */
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <0>;
|
||||
cell-index = <2>;
|
||||
reg = <0x2400 0x100>;
|
||||
interrupts = <0x2 0x3 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <2 3 0>;
|
||||
};
|
||||
|
||||
/* PSC4 is ??? */
|
||||
@@ -238,55 +206,44 @@
|
||||
/* PSC5 is ??? */
|
||||
|
||||
serial@2c00 { /* PSC6 in UART mode */
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
|
||||
port-number = <1>;
|
||||
cell-index = <5>;
|
||||
reg = <0x2c00 0x100>;
|
||||
interrupts = <0x2 0x4 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <2 4 0>;
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
interrupts = <0x2 0x5 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
mdio@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
|
||||
reg = <0x3000 0x400>; /* fec range, since we need to setup fec interrupts */
|
||||
interrupts = <0x2 0x5 0x0>; /* these are for "mii command finished", not link changes & co. */
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
|
||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
|
||||
phy0:ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0x0>;
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ata@3a00 {
|
||||
device_type = "ata";
|
||||
compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <0x2 0x7 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <2 7 0>;
|
||||
};
|
||||
|
||||
i2c@3d00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <0>;
|
||||
reg = <0x3d00 0x40>;
|
||||
interrupts = <0x2 0xf 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <2 15 0>;
|
||||
fsl5200-clocking;
|
||||
};
|
||||
|
||||
@@ -294,10 +251,8 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
|
||||
cell-index = <1>;
|
||||
reg = <0x3d40 0x40>;
|
||||
interrupts = <0x2 0x10 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <2 16 0>;
|
||||
fsl5200-clocking;
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
@@ -307,7 +262,7 @@
|
||||
};
|
||||
|
||||
sram@8000 {
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
|
||||
compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
|
||||
reg = <0x8000 0x4000>;
|
||||
};
|
||||
|
||||
@@ -340,22 +295,21 @@
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
|
||||
reg = <0xf0000d00 0x100>;
|
||||
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
||||
interrupt-map = <0xc000 0x0 0x0 0x1 &mpc5200_pic 0x0 0x0 0x3 /* 1st slot */
|
||||
0xc000 0x0 0x0 0x2 &mpc5200_pic 0x1 0x1 0x3
|
||||
0xc000 0x0 0x0 0x3 &mpc5200_pic 0x1 0x2 0x3
|
||||
0xc000 0x0 0x0 0x4 &mpc5200_pic 0x1 0x3 0x3
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
|
||||
0xc000 0 0 2 &mpc5200_pic 1 1 3
|
||||
0xc000 0 0 3 &mpc5200_pic 1 2 3
|
||||
0xc000 0 0 4 &mpc5200_pic 1 3 3
|
||||
|
||||
0xc800 0x0 0x0 0x1 &mpc5200_pic 0x1 0x1 0x3 /* 2nd slot */
|
||||
0xc800 0x0 0x0 0x2 &mpc5200_pic 0x1 0x2 0x3
|
||||
0xc800 0x0 0x0 0x3 &mpc5200_pic 0x1 0x3 0x3
|
||||
0xc800 0x0 0x0 0x4 &mpc5200_pic 0x0 0x0 0x3>;
|
||||
0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
|
||||
0xc800 0 0 2 &mpc5200_pic 1 2 3
|
||||
0xc800 0 0 3 &mpc5200_pic 1 3 3
|
||||
0xc800 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <0x2 0x8 0x0 0x2 0x9 0x0 0x2 0xa 0x0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
|
||||
0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
|
||||
0x01000000 0x0 0x00000000 0xb0000000 0x0 0x01000000>;
|
||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
|
||||
0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -17,6 +17,7 @@
|
||||
compatible = "tqc,tqm5200";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
@@ -66,36 +67,33 @@
|
||||
compatible = "fsl,mpc5200-gpt";
|
||||
reg = <0x600 0x10>;
|
||||
interrupts = <1 9 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl,has-wdt;
|
||||
};
|
||||
|
||||
can@900 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
interrupts = <2 17 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <0x900 0x80>;
|
||||
};
|
||||
|
||||
can@980 {
|
||||
compatible = "fsl,mpc5200-mscan";
|
||||
interrupts = <2 18 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
reg = <0x980 0x80>;
|
||||
};
|
||||
|
||||
gpio@b00 {
|
||||
gpio_simple: gpio@b00 {
|
||||
compatible = "fsl,mpc5200-gpio";
|
||||
reg = <0xb00 0x40>;
|
||||
interrupts = <1 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
usb@1000 {
|
||||
compatible = "fsl,mpc5200-ohci","ohci-be";
|
||||
reg = <0x1000 0xff>;
|
||||
interrupts = <2 6 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
dma-controller@1200 {
|
||||
@@ -105,7 +103,6 @@
|
||||
3 4 0 3 5 0 3 6 0 3 7 0
|
||||
3 8 0 3 9 0 3 10 0 3 11 0
|
||||
3 12 0 3 13 0 3 14 0 3 15 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
xlb@1f00 {
|
||||
@@ -114,39 +111,28 @@
|
||||
};
|
||||
|
||||
serial@2000 { // PSC1
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <0>; // Logical port assignment
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <2 1 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
serial@2200 { // PSC2
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <1>; // Logical port assignment
|
||||
reg = <0x2200 0x100>;
|
||||
interrupts = <2 2 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
serial@2400 { // PSC3
|
||||
device_type = "serial";
|
||||
compatible = "fsl,mpc5200-psc-uart";
|
||||
port-number = <2>; // Logical port assignment
|
||||
reg = <0x2400 0x100>;
|
||||
interrupts = <2 3 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
ethernet@3000 {
|
||||
device_type = "network";
|
||||
compatible = "fsl,mpc5200-fec";
|
||||
reg = <0x3000 0x400>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <2 5 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
@@ -156,10 +142,8 @@
|
||||
compatible = "fsl,mpc5200-mdio";
|
||||
reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
|
||||
interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
device_type = "ethernet-phy";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
@@ -168,7 +152,6 @@
|
||||
compatible = "fsl,mpc5200-ata";
|
||||
reg = <0x3a00 0x100>;
|
||||
interrupts = <2 7 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
};
|
||||
|
||||
i2c@3d40 {
|
||||
@@ -177,7 +160,6 @@
|
||||
compatible = "fsl,mpc5200-i2c","fsl-i2c";
|
||||
reg = <0x3d40 0x40>;
|
||||
interrupts = <2 16 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
fsl5200-clocking;
|
||||
|
||||
rtc@68 {
|
||||
@@ -192,9 +174,8 @@
|
||||
};
|
||||
};
|
||||
|
||||
lpb {
|
||||
model = "fsl,lpb";
|
||||
compatible = "fsl,lpb";
|
||||
localbus {
|
||||
compatible = "fsl,mpc5200-lpb","simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0xfc000000 0x02000000>;
|
||||
@@ -223,7 +204,6 @@
|
||||
0xc000 0 0 4 &mpc5200_pic 0 0 3>;
|
||||
clock-frequency = <0>; // From boot loader
|
||||
interrupts = <2 8 0 2 9 0 2 10 0>;
|
||||
interrupt-parent = <&mpc5200_pic>;
|
||||
bus-range = <0 0>;
|
||||
ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000
|
||||
0x02000000 0 0x90000000 0x90000000 0 0x10000000
|
||||
|
||||
Reference in New Issue
Block a user