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powerpc: Add SPE/EFP math emulation for E500v1/v2 processors.

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This patch add the handlers of SPE/EFP exceptions.
The code is used to emulate float point arithmetic,
when MSR(SPE) is enabled and receive EFP data interrupt or EFP round interrupt.

This patch has no conflict with or dependence on FP math-emu.

The code has been tested by TestFloat.

Now the code doesn't support SPE/EFP instructions emulation
(it won't be called when receive program interrupt),
but it could be easily added.

Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Liu Yu
2008-10-28 11:50:21 +08:00
committed by Kumar Gala
parent 033b8a333c
commit 6a800f36ac
6 changed files with 813 additions and 20 deletions
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36
arch/powerpc/include/asm/sfp-machine.h
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@@ -97,6 +97,20 @@
#define _FP_KEEPNANFRACP 1
#ifdef FP_EX_BOOKE_E500_SPE
#define FP_EX_INEXACT (1 << 21)
#define FP_EX_INVALID (1 << 20)
#define FP_EX_DIVZERO (1 << 19)
#define FP_EX_UNDERFLOW (1 << 18)
#define FP_EX_OVERFLOW (1 << 17)
#define FP_INHIBIT_RESULTS 0
#define __FPU_FPSCR (current->thread.spefscr)
#define __FPU_ENABLED_EXC \
({ \
(__FPU_FPSCR >> 2) & 0x1f; \
})
#else
/* Exception flags. We use the bit positions of the appropriate bits
in the FPSCR, which also correspond to the FE_* bits. This makes
everything easier ;-). */
@@ -111,6 +125,18 @@
#define FP_EX_DIVZERO (1 << (31 - 5))
#define FP_EX_INEXACT (1 << (31 - 6))
#define __FPU_FPSCR (current->thread.fpscr.val)
/* We only actually write to the destination register
* if exceptions signalled (if any) will not trap.
*/
#define __FPU_ENABLED_EXC \
({ \
(__FPU_FPSCR >> 3) & 0x1f; \
})
#endif
/*
* If one NaN is signaling and the other is not,
* we choose that one, otherwise we choose X.
@@ -135,16 +161,6 @@
#include <linux/kernel.h>
#include <linux/sched.h>
#define __FPU_FPSCR (current->thread.fpscr.val)
/* We only actually write to the destination register
* if exceptions signalled (if any) will not trap.
*/
#define __FPU_ENABLED_EXC \
({ \
(__FPU_FPSCR >> 3) & 0x1f; \
})
#define __FPU_TRAP_P(bits) \
((__FPU_ENABLED_EXC & (bits)) != 0)