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drivers/net: Trim trailing whitespace

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Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Jeff Garzik
2006-09-13 13:24:59 -04:00
parent 7a29108322
commit 6aa20a2235
178 changed files with 22402 additions and 22402 deletions
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18
drivers/net/sis900.h
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@@ -1,4 +1,4 @@
/* sis900.h Definitions for SiS ethernet controllers including 7014/7016 and 900
/* sis900.h Definitions for SiS ethernet controllers including 7014/7016 and 900
* Copyright 1999 Silicon Integrated System Corporation
* References:
* SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
@@ -49,7 +49,7 @@ enum sis900_command_register_bits {
enum sis900_configuration_register_bits {
DESCRFMT = 0x00000100 /* 7016 specific */, REQALG = 0x00000080,
SB = 0x00000040, POW = 0x00000020, EXD = 0x00000010,
SB = 0x00000040, POW = 0x00000020, EXD = 0x00000010,
PESEL = 0x00000008, LPM = 0x00000004, BEM = 0x00000001,
/* 635 & 900B Specific */
RND_CNT = 0x00000400, FAIR_BACKOFF = 0x00000200,
@@ -57,7 +57,7 @@ enum sis900_configuration_register_bits {
};
enum sis900_eeprom_access_reigster_bits {
MDC = 0x00000040, MDDIR = 0x00000020, MDIO = 0x00000010, /* 7016 specific */
MDC = 0x00000040, MDDIR = 0x00000020, MDIO = 0x00000010, /* 7016 specific */
EECS = 0x00000008, EECLK = 0x00000004, EEDO = 0x00000002,
EEDI = 0x00000001
};
@@ -129,9 +129,9 @@ enum sis900_eeprom_address {
/* The EEPROM commands include the alway-set leading bit. Refer to NM93Cxx datasheet */
enum sis900_eeprom_command {
EEread = 0x0180, EEwrite = 0x0140, EEerase = 0x01C0,
EEread = 0x0180, EEwrite = 0x0140, EEerase = 0x01C0,
EEwriteEnable = 0x0130, EEwriteDisable = 0x0100,
EEeraseAll = 0x0120, EEwriteAll = 0x0110,
EEeraseAll = 0x0120, EEwriteAll = 0x0110,
EEaddrMask = 0x013F, EEcmdShift = 16
};
@@ -148,7 +148,7 @@ enum sis900_pci_registers {
/* Power management capabilities bits */
enum sis900_cfgpmc_register_bits {
PMVER = 0x00070000,
PMVER = 0x00070000,
DSI = 0x00100000,
PMESP = 0xf8000000
};
@@ -238,7 +238,7 @@ enum amd_mii_registers {
/* MII Control register bit definitions. */
enum mii_control_register_bits {
MII_CNTL_FDX = 0x0100, MII_CNTL_RST_AUTO = 0x0200,
MII_CNTL_FDX = 0x0100, MII_CNTL_RST_AUTO = 0x0200,
MII_CNTL_ISOLATE = 0x0400, MII_CNTL_PWRDWN = 0x0800,
MII_CNTL_AUTO = 0x1000, MII_CNTL_SPEED = 0x2000,
MII_CNTL_LPBK = 0x4000, MII_CNTL_RESET = 0x8000
@@ -246,8 +246,8 @@ enum mii_control_register_bits {
/* MII Status register bit */
enum mii_status_register_bits {
MII_STAT_EXT = 0x0001, MII_STAT_JAB = 0x0002,
MII_STAT_LINK = 0x0004, MII_STAT_CAN_AUTO = 0x0008,
MII_STAT_EXT = 0x0001, MII_STAT_JAB = 0x0002,
MII_STAT_LINK = 0x0004, MII_STAT_CAN_AUTO = 0x0008,
MII_STAT_FAULT = 0x0010, MII_STAT_AUTO_DONE = 0x0020,
MII_STAT_CAN_T = 0x0800, MII_STAT_CAN_T_FDX = 0x1000,
MII_STAT_CAN_TX = 0x2000, MII_STAT_CAN_TX_FDX = 0x4000,