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MIPS: Add HARDWARE_WATCHPOINTS definitions and support code.

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This is the main support code for the patch.  Here we just add the
code, the following patches hook it up.

Signed-off-by: David Daney <ddaney@avtrex.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

 create mode 100644 arch/mips/include/asm/watch.h
 create mode 100644 arch/mips/kernel/watch.c
This commit is contained in:
David Daney
2008-09-23 00:05:54 -07:00
committed by Ralf Baechle
parent 8192c9ea9a
commit 6aa3524c18
6 changed files with 249 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/mips/include/asm/cpu-info.h
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@ -12,6 +12,8 @@
#ifndef __ASM_CPU_INFO_H
#define __ASM_CPU_INFO_H
#include <linux/types.h>
#include <asm/cache.h>
/*
@ -69,6 +71,10 @@ struct cpuinfo_mips {
int tc_id; /* Thread Context number */
#endif
void *data; /* Additional data */
unsigned int watch_reg_count; /* Number that exist */
unsigned int watch_reg_use_cnt; /* Usable by ptrace */
#define NUM_WATCH_REGS 4
u16 watch_reg_masks[NUM_WATCH_REGS];
} __attribute__((aligned(SMP_CACHE_BYTES)));
extern struct cpuinfo_mips cpu_data[];

20
arch/mips/include/asm/processor.h
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@ -105,6 +105,19 @@ struct mips_dsp_state {
{0,} \
}
struct mips3264_watch_reg_state {
/* The width of watchlo is 32 in a 32 bit kernel and 64 in a
64 bit kernel. We use unsigned long as it has the same
property. */
unsigned long watchlo[NUM_WATCH_REGS];
/* Only the mask and IRW bits from watchhi. */
u16 watchhi[NUM_WATCH_REGS];
};
union mips_watch_reg_state {
struct mips3264_watch_reg_state mips3264;
};
typedef struct {
unsigned long seg;
} mm_segment_t;
@ -137,6 +150,9 @@ struct thread_struct {
/* Saved state of the DSP ASE, if available. */
struct mips_dsp_state dsp;
/* Saved watch register state, if available. */
union mips_watch_reg_state watch;
/* Other stuff associated with the thread. */
unsigned long cp0_badvaddr; /* Last user fault */
unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
@ -192,6 +208,10 @@ struct thread_struct {
.dspr = {0, }, \
.dspcontrol = 0, \
}, \
/* \
* saved watch register stuff \
*/ \
.watch = {{{0,},},}, \
/* \
* Other stuff associated with the process \
*/ \

2
arch/mips/include/asm/thread_info.h
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@ -124,6 +124,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
#define TIF_32BIT_REGS 22 /* also implies 16/32 fprs */
#define TIF_32BIT_ADDR 23 /* 32-bit address space (o32/n32) */
#define TIF_FPUBOUND 24 /* thread bound to FPU-full CPU set */
#define TIF_LOAD_WATCH 25 /* If set, load watch registers */
#define TIF_SYSCALL_TRACE 31 /* syscall trace active */
#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@ -140,6 +141,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
#define _TIF_32BIT_REGS (1<<TIF_32BIT_REGS)
#define _TIF_32BIT_ADDR (1<<TIF_32BIT_ADDR)
#define _TIF_FPUBOUND (1<<TIF_FPUBOUND)
#define _TIF_LOAD_WATCH (1<<TIF_LOAD_WATCH)
/* work to do on interrupt/exception return */
#define _TIF_WORK_MASK (0x0000ffef & ~_TIF_SECCOMP)

32
arch/mips/include/asm/watch.h Normal file
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@ -0,0 +1,32 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2008 David Daney
*/
#ifndef _ASM_WATCH_H
#define _ASM_WATCH_H
#include <linux/bitops.h>
#include <asm/mipsregs.h>
void mips_install_watch_registers(void);
void mips_read_watch_registers(void);
void mips_clear_watch_registers(void);
void mips_probe_watch_registers(struct cpuinfo_mips *c);
#ifdef CONFIG_HARDWARE_WATCHPOINTS
#define __restore_watch() do { \
if (unlikely(test_bit(TIF_LOAD_WATCH, \
&current_thread_info()->flags))) { \
mips_install_watch_registers(); \
} \
} while (0)
#else
#define __restore_watch() do {} while (0)
#endif
#endif /* _ASM_WATCH_H */