MIPS: Add HARDWARE_WATCHPOINTS definitions and support code.
This is the main support code for the patch. Here we just add the code, the following patches hook it up. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/include/asm/watch.h create mode 100644 arch/mips/kernel/watch.c
This commit is contained in:
David Daney
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Ralf Baechle
Ralf Baechle
parent
8192c9ea9a
commit
6aa3524c18
188
arch/mips/kernel/watch.c
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188
arch/mips/kernel/watch.c
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 David Daney
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*/
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#include <linux/sched.h>
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#include <asm/processor.h>
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#include <asm/watch.h>
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/*
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* Install the watch registers for the current thread. A maximum of
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* four registers are installed although the machine may have more.
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*/
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void mips_install_watch_registers(void)
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{
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struct mips3264_watch_reg_state *watches =
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¤t->thread.watch.mips3264;
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switch (current_cpu_data.watch_reg_use_cnt) {
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default:
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BUG();
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case 4:
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write_c0_watchlo3(watches->watchlo[3]);
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/* Write 1 to the I, R, and W bits to clear them, and
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1 to G so all ASIDs are trapped. */
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write_c0_watchhi3(0x40000007 | watches->watchhi[3]);
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case 3:
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write_c0_watchlo2(watches->watchlo[2]);
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write_c0_watchhi2(0x40000007 | watches->watchhi[2]);
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case 2:
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write_c0_watchlo1(watches->watchlo[1]);
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write_c0_watchhi1(0x40000007 | watches->watchhi[1]);
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case 1:
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write_c0_watchlo0(watches->watchlo[0]);
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write_c0_watchhi0(0x40000007 | watches->watchhi[0]);
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}
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}
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/*
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* Read back the watchhi registers so the user space debugger has
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* access to the I, R, and W bits. A maximum of four registers are
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* read although the machine may have more.
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*/
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void mips_read_watch_registers(void)
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{
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struct mips3264_watch_reg_state *watches =
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¤t->thread.watch.mips3264;
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switch (current_cpu_data.watch_reg_use_cnt) {
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default:
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BUG();
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case 4:
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watches->watchhi[3] = (read_c0_watchhi3() & 0x0fff);
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case 3:
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watches->watchhi[2] = (read_c0_watchhi2() & 0x0fff);
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case 2:
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watches->watchhi[1] = (read_c0_watchhi1() & 0x0fff);
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case 1:
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watches->watchhi[0] = (read_c0_watchhi0() & 0x0fff);
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}
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if (current_cpu_data.watch_reg_use_cnt == 1 &&
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(watches->watchhi[0] & 7) == 0) {
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/* Pathological case of release 1 architecture that
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* doesn't set the condition bits. We assume that
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* since we got here, the watch condition was met and
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* signal that the conditions requested in watchlo
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* were met. */
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watches->watchhi[0] |= (watches->watchlo[0] & 7);
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}
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}
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/*
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* Disable all watch registers. Although only four registers are
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* installed, all are cleared to eliminate the possibility of endless
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* looping in the watch handler.
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*/
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void mips_clear_watch_registers(void)
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{
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switch (current_cpu_data.watch_reg_count) {
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default:
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BUG();
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case 8:
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write_c0_watchlo7(0);
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case 7:
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write_c0_watchlo6(0);
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case 6:
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write_c0_watchlo5(0);
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case 5:
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write_c0_watchlo4(0);
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case 4:
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write_c0_watchlo3(0);
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case 3:
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write_c0_watchlo2(0);
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case 2:
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write_c0_watchlo1(0);
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case 1:
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write_c0_watchlo0(0);
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}
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}
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__cpuinit void mips_probe_watch_registers(struct cpuinfo_mips *c)
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{
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unsigned int t;
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if ((c->options & MIPS_CPU_WATCH) == 0)
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return;
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/*
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* Check which of the I,R and W bits are supported, then
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* disable the register.
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*/
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write_c0_watchlo0(7);
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t = read_c0_watchlo0();
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write_c0_watchlo0(0);
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c->watch_reg_masks[0] = t & 7;
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/* Write the mask bits and read them back to determine which
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* can be used. */
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c->watch_reg_count = 1;
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c->watch_reg_use_cnt = 1;
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t = read_c0_watchhi0();
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write_c0_watchhi0(t | 0xff8);
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t = read_c0_watchhi0();
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c->watch_reg_masks[0] |= (t & 0xff8);
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if ((t & 0x80000000) == 0)
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return;
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write_c0_watchlo1(7);
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t = read_c0_watchlo1();
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write_c0_watchlo1(0);
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c->watch_reg_masks[1] = t & 7;
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c->watch_reg_count = 2;
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c->watch_reg_use_cnt = 2;
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t = read_c0_watchhi1();
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write_c0_watchhi1(t | 0xff8);
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t = read_c0_watchhi1();
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c->watch_reg_masks[1] |= (t & 0xff8);
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if ((t & 0x80000000) == 0)
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return;
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write_c0_watchlo2(7);
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t = read_c0_watchlo2();
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write_c0_watchlo2(0);
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c->watch_reg_masks[2] = t & 7;
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c->watch_reg_count = 3;
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c->watch_reg_use_cnt = 3;
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t = read_c0_watchhi2();
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write_c0_watchhi2(t | 0xff8);
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t = read_c0_watchhi2();
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c->watch_reg_masks[2] |= (t & 0xff8);
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if ((t & 0x80000000) == 0)
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return;
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write_c0_watchlo3(7);
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t = read_c0_watchlo3();
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write_c0_watchlo3(0);
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c->watch_reg_masks[3] = t & 7;
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c->watch_reg_count = 4;
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c->watch_reg_use_cnt = 4;
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t = read_c0_watchhi3();
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write_c0_watchhi3(t | 0xff8);
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t = read_c0_watchhi3();
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c->watch_reg_masks[3] |= (t & 0xff8);
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if ((t & 0x80000000) == 0)
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return;
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/* We use at most 4, but probe and report up to 8. */
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c->watch_reg_count = 5;
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t = read_c0_watchhi4();
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if ((t & 0x80000000) == 0)
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return;
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c->watch_reg_count = 6;
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t = read_c0_watchhi5();
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if ((t & 0x80000000) == 0)
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return;
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c->watch_reg_count = 7;
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t = read_c0_watchhi6();
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if ((t & 0x80000000) == 0)
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return;
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c->watch_reg_count = 8;
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}
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