[POWERPC] qe: miscellaneous code improvements and fixes to the QE library
This patch makes numerous miscellaneous code improvements to the QE library.
1. Remove struct ucc_common and merge ucc_init_guemr() into ucc_set_type()
(every caller of ucc_init_guemr() also calls ucc_set_type()). Modify all
callers of ucc_set_type() accordingly.
2. Remove the unused enum ucc_pram_initial_offset.
3. Refactor qe_setbrg(), also implement work-around for errata QE_General4.
4. Several printk() calls were missing the terminating \n.
5. Add __iomem where needed, and change u16 to __be16 and u32 to __be32 where
appropriate.
6. In ucc_slow_init() the RBASE and TBASE registers in the PRAM were programmed
with the wrong value.
7. Add the protocol type to struct us_info and updated ucc_slow_init() to
use it, instead of always programming QE_CR_PROTOCOL_UNSPECIFIED.
8. Rename ucc_slow_restart_x() to ucc_slow_restart_tx()
9. Add several macros in qe.h (mostly for slow UCC support, but also to
standardize some naming convention) and remove several unused macros.
10. Update ucc_geth.c to use the new macros.
11. Add ucc_slow_info.protocol to specify which QE_CR_PROTOCOL_xxx protcol
to use when initializing the UCC in ucc_slow_init().
12. Rename ucc_slow_pram.rfcr to rbmr and ucc_slow_pram.tfcr to tbmr, since
these are the real names of the registers.
13. Use the setbits, clrbits, and clrsetbits where appropriate.
14. Refactor ucc_set_qe_mux_rxtx().
15. Remove all instances of 'volatile'.
16. Simplify get_cmxucr_reg();
17. Replace qe_mux.cmxucrX with qe_mux.cmxucr[].
18. Updated struct ucc_geth because struct ucc_fast is not padded any more.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Timur Tabi
Kumar Gala
@@ -28,228 +28,188 @@
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static DEFINE_SPINLOCK(ucc_lock);
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int ucc_set_qe_mux_mii_mng(int ucc_num)
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int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
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{
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unsigned long flags;
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if (ucc_num > UCC_MAX_NUM - 1)
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return -EINVAL;
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spin_lock_irqsave(&ucc_lock, flags);
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out_be32(&qe_immr->qmx.cmxgcr,
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((in_be32(&qe_immr->qmx.cmxgcr) &
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~QE_CMXGCR_MII_ENET_MNG) |
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(ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT)));
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clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
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ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
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spin_unlock_irqrestore(&ucc_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(ucc_set_qe_mux_mii_mng);
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int ucc_set_type(int ucc_num, struct ucc_common *regs,
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enum ucc_speed_type speed)
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/* Configure the UCC to either Slow or Fast.
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*
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* A given UCC can be figured to support either "slow" devices (e.g. UART)
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* or "fast" devices (e.g. Ethernet).
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*
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* 'ucc_num' is the UCC number, from 0 - 7.
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*
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* This function also sets the UCC_GUEMR_SET_RESERVED3 bit because that bit
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* must always be set to 1.
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*/
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int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
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{
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u8 guemr = 0;
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u8 __iomem *guemr;
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/* check if the UCC number is in range. */
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if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
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return -EINVAL;
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guemr = regs->guemr;
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guemr &= ~(UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX);
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switch (speed) {
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case UCC_SPEED_TYPE_SLOW:
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guemr |= (UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX);
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break;
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case UCC_SPEED_TYPE_FAST:
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guemr |= (UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX);
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break;
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default:
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return -EINVAL;
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}
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regs->guemr = guemr;
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return 0;
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}
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int ucc_init_guemr(struct ucc_common *regs)
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{
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u8 guemr = 0;
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if (!regs)
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return -EINVAL;
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/* Set bit 3 (which is reserved in the GUEMR register) to 1 */
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guemr = UCC_GUEMR_SET_RESERVED3;
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regs->guemr = guemr;
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return 0;
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}
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static void get_cmxucr_reg(int ucc_num, volatile u32 ** p_cmxucr, u8 * reg_num,
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u8 * shift)
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{
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/* The GUEMR register is at the same location for both slow and fast
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devices, so we just use uccX.slow.guemr. */
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switch (ucc_num) {
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case 0: *p_cmxucr = &(qe_immr->qmx.cmxucr1);
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*reg_num = 1;
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*shift = 16;
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case 0: guemr = &qe_immr->ucc1.slow.guemr;
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break;
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case 2: *p_cmxucr = &(qe_immr->qmx.cmxucr1);
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*reg_num = 1;
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*shift = 0;
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case 1: guemr = &qe_immr->ucc2.slow.guemr;
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break;
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case 4: *p_cmxucr = &(qe_immr->qmx.cmxucr2);
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*reg_num = 2;
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*shift = 16;
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case 2: guemr = &qe_immr->ucc3.slow.guemr;
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break;
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case 6: *p_cmxucr = &(qe_immr->qmx.cmxucr2);
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*reg_num = 2;
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*shift = 0;
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case 3: guemr = &qe_immr->ucc4.slow.guemr;
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break;
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case 1: *p_cmxucr = &(qe_immr->qmx.cmxucr3);
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*reg_num = 3;
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*shift = 16;
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case 4: guemr = &qe_immr->ucc5.slow.guemr;
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break;
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case 3: *p_cmxucr = &(qe_immr->qmx.cmxucr3);
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*reg_num = 3;
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*shift = 0;
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case 5: guemr = &qe_immr->ucc6.slow.guemr;
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break;
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case 5: *p_cmxucr = &(qe_immr->qmx.cmxucr4);
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*reg_num = 4;
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*shift = 16;
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case 6: guemr = &qe_immr->ucc7.slow.guemr;
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break;
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case 7: *p_cmxucr = &(qe_immr->qmx.cmxucr4);
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*reg_num = 4;
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*shift = 0;
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case 7: guemr = &qe_immr->ucc8.slow.guemr;
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break;
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default:
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break;
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return -EINVAL;
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}
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clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
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UCC_GUEMR_SET_RESERVED3 | speed);
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return 0;
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}
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int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask)
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static void get_cmxucr_reg(unsigned int ucc_num, __be32 **cmxucr,
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unsigned int *reg_num, unsigned int *shift)
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{
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volatile u32 *p_cmxucr;
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u8 reg_num;
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u8 shift;
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unsigned int cmx = ((ucc_num & 1) << 1) + (ucc_num > 3);
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*reg_num = cmx + 1;
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*cmxucr = &qe_immr->qmx.cmxucr[cmx];
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*shift = 16 - 8 * (ucc_num & 2);
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}
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int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
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{
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__be32 *cmxucr;
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unsigned int reg_num;
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unsigned int shift;
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/* check if the UCC number is in range. */
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if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
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if (ucc_num > UCC_MAX_NUM - 1)
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return -EINVAL;
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get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift);
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get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
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if (set)
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out_be32(p_cmxucr, in_be32(p_cmxucr) | (mask << shift));
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setbits32(cmxucr, mask << shift);
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else
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out_be32(p_cmxucr, in_be32(p_cmxucr) & ~(mask << shift));
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clrbits32(cmxucr, mask << shift);
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return 0;
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}
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int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode)
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int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
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enum comm_dir mode)
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{
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volatile u32 *p_cmxucr;
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u8 reg_num;
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u8 shift;
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u32 clock_bits;
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u32 clock_mask;
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int source = -1;
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__be32 *cmxucr;
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unsigned int reg_num;
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unsigned int shift;
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u32 clock_bits = 0;
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/* check if the UCC number is in range. */
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if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0))
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if (ucc_num > UCC_MAX_NUM - 1)
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return -EINVAL;
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if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) {
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printk(KERN_ERR
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"ucc_set_qe_mux_rxtx: bad comm mode type passed.");
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/* The communications direction must be RX or TX */
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if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX)))
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return -EINVAL;
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}
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get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift);
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get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
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switch (reg_num) {
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case 1:
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switch (clock) {
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case QE_BRG1: source = 1; break;
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case QE_BRG2: source = 2; break;
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case QE_BRG7: source = 3; break;
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case QE_BRG8: source = 4; break;
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case QE_CLK9: source = 5; break;
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case QE_CLK10: source = 6; break;
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case QE_CLK11: source = 7; break;
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case QE_CLK12: source = 8; break;
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case QE_CLK15: source = 9; break;
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case QE_CLK16: source = 10; break;
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default: source = -1; break;
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case QE_BRG1: clock_bits = 1; break;
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case QE_BRG2: clock_bits = 2; break;
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case QE_BRG7: clock_bits = 3; break;
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case QE_BRG8: clock_bits = 4; break;
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case QE_CLK9: clock_bits = 5; break;
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case QE_CLK10: clock_bits = 6; break;
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case QE_CLK11: clock_bits = 7; break;
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case QE_CLK12: clock_bits = 8; break;
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case QE_CLK15: clock_bits = 9; break;
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case QE_CLK16: clock_bits = 10; break;
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default: break;
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}
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break;
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case 2:
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switch (clock) {
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case QE_BRG5: source = 1; break;
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case QE_BRG6: source = 2; break;
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case QE_BRG7: source = 3; break;
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case QE_BRG8: source = 4; break;
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case QE_CLK13: source = 5; break;
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case QE_CLK14: source = 6; break;
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case QE_CLK19: source = 7; break;
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case QE_CLK20: source = 8; break;
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case QE_CLK15: source = 9; break;
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case QE_CLK16: source = 10; break;
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default: source = -1; break;
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case QE_BRG5: clock_bits = 1; break;
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case QE_BRG6: clock_bits = 2; break;
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case QE_BRG7: clock_bits = 3; break;
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case QE_BRG8: clock_bits = 4; break;
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case QE_CLK13: clock_bits = 5; break;
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case QE_CLK14: clock_bits = 6; break;
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case QE_CLK19: clock_bits = 7; break;
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case QE_CLK20: clock_bits = 8; break;
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case QE_CLK15: clock_bits = 9; break;
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case QE_CLK16: clock_bits = 10; break;
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default: break;
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}
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break;
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case 3:
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switch (clock) {
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case QE_BRG9: source = 1; break;
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case QE_BRG10: source = 2; break;
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case QE_BRG15: source = 3; break;
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case QE_BRG16: source = 4; break;
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case QE_CLK3: source = 5; break;
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case QE_CLK4: source = 6; break;
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case QE_CLK17: source = 7; break;
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case QE_CLK18: source = 8; break;
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case QE_CLK7: source = 9; break;
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case QE_CLK8: source = 10; break;
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case QE_CLK16: source = 11; break;
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default: source = -1; break;
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case QE_BRG9: clock_bits = 1; break;
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case QE_BRG10: clock_bits = 2; break;
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case QE_BRG15: clock_bits = 3; break;
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case QE_BRG16: clock_bits = 4; break;
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case QE_CLK3: clock_bits = 5; break;
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case QE_CLK4: clock_bits = 6; break;
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case QE_CLK17: clock_bits = 7; break;
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case QE_CLK18: clock_bits = 8; break;
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case QE_CLK7: clock_bits = 9; break;
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case QE_CLK8: clock_bits = 10; break;
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case QE_CLK16: clock_bits = 11; break;
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default: break;
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}
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break;
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case 4:
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switch (clock) {
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case QE_BRG13: source = 1; break;
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case QE_BRG14: source = 2; break;
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case QE_BRG15: source = 3; break;
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case QE_BRG16: source = 4; break;
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case QE_CLK5: source = 5; break;
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case QE_CLK6: source = 6; break;
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case QE_CLK21: source = 7; break;
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case QE_CLK22: source = 8; break;
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case QE_CLK7: source = 9; break;
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case QE_CLK8: source = 10; break;
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case QE_CLK16: source = 11; break;
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default: source = -1; break;
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case QE_BRG13: clock_bits = 1; break;
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case QE_BRG14: clock_bits = 2; break;
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case QE_BRG15: clock_bits = 3; break;
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case QE_BRG16: clock_bits = 4; break;
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case QE_CLK5: clock_bits = 5; break;
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case QE_CLK6: clock_bits = 6; break;
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case QE_CLK21: clock_bits = 7; break;
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case QE_CLK22: clock_bits = 8; break;
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case QE_CLK7: clock_bits = 9; break;
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case QE_CLK8: clock_bits = 10; break;
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case QE_CLK16: clock_bits = 11; break;
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default: break;
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}
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break;
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default:
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source = -1;
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break;
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default: break;
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}
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if (source == -1) {
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printk(KERN_ERR
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"ucc_set_qe_mux_rxtx: Bad combination of clock and UCC.");
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/* Check for invalid combination of clock and UCC number */
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if (!clock_bits)
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return -ENOENT;
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}
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clock_bits = (u32) source;
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clock_mask = QE_CMXUCR_TX_CLK_SRC_MASK;
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if (mode == COMM_DIR_RX) {
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clock_bits <<= 4; /* Rx field is 4 bits to left of Tx field */
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clock_mask <<= 4; /* Rx field is 4 bits to left of Tx field */
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}
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clock_bits <<= shift;
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clock_mask <<= shift;
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if (mode == COMM_DIR_RX)
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shift += 4;
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out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clock_mask) | clock_bits);
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clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
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clock_bits << shift);
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return 0;
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}
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