Blackfin arch: SMP supporting patchset: Blackfin header files and machine common code
Blackfin dual core BF561 processor can support SMP like features. https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like In this patch, we provide SMP extend to Blackfin header files and machine common code Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
This commit is contained in:
Graf Yang
Bryan Wu
@ -7,7 +7,6 @@
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#include <linux/compiler.h>
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#include <asm/byteorder.h> /* swab32 */
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#include <asm/system.h> /* save_flags */
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#ifdef __KERNEL__
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@ -20,12 +19,75 @@
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/ffz.h>
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static __inline__ void set_bit(int nr, volatile unsigned long *addr)
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#ifdef CONFIG_SMP
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#include <linux/linkage.h>
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asmlinkage int __raw_bit_set_asm(volatile unsigned long *addr, int nr);
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asmlinkage int __raw_bit_clear_asm(volatile unsigned long *addr, int nr);
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asmlinkage int __raw_bit_toggle_asm(volatile unsigned long *addr, int nr);
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asmlinkage int __raw_bit_test_set_asm(volatile unsigned long *addr, int nr);
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asmlinkage int __raw_bit_test_clear_asm(volatile unsigned long *addr, int nr);
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asmlinkage int __raw_bit_test_toggle_asm(volatile unsigned long *addr, int nr);
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asmlinkage int __raw_bit_test_asm(const volatile unsigned long *addr, int nr);
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static inline void set_bit(int nr, volatile unsigned long *addr)
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{
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volatile unsigned long *a = addr + (nr >> 5);
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__raw_bit_set_asm(a, nr & 0x1f);
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}
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static inline void clear_bit(int nr, volatile unsigned long *addr)
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{
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volatile unsigned long *a = addr + (nr >> 5);
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__raw_bit_clear_asm(a, nr & 0x1f);
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}
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static inline void change_bit(int nr, volatile unsigned long *addr)
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{
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volatile unsigned long *a = addr + (nr >> 5);
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__raw_bit_toggle_asm(a, nr & 0x1f);
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}
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static inline int test_bit(int nr, const volatile unsigned long *addr)
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{
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volatile const unsigned long *a = addr + (nr >> 5);
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return __raw_bit_test_asm(a, nr & 0x1f) != 0;
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}
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static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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volatile unsigned long *a = addr + (nr >> 5);
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return __raw_bit_test_set_asm(a, nr & 0x1f);
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}
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static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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volatile unsigned long *a = addr + (nr >> 5);
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return __raw_bit_test_clear_asm(a, nr & 0x1f);
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}
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static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
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{
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volatile unsigned long *a = addr + (nr >> 5);
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return __raw_bit_test_toggle_asm(a, nr & 0x1f);
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}
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#else /* !CONFIG_SMP */
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#include <asm/system.h> /* save_flags */
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static inline void set_bit(int nr, volatile unsigned long *addr)
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{
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int *a = (int *)addr;
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int mask;
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unsigned long flags;
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a += nr >> 5;
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mask = 1 << (nr & 0x1f);
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local_irq_save(flags);
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@ -33,23 +95,7 @@ static __inline__ void set_bit(int nr, volatile unsigned long *addr)
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local_irq_restore(flags);
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}
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static __inline__ void __set_bit(int nr, volatile unsigned long *addr)
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{
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int *a = (int *)addr;
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int mask;
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a += nr >> 5;
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mask = 1 << (nr & 0x1f);
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*a |= mask;
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}
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/*
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* clear_bit() doesn't provide any barrier for the compiler.
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*/
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#define smp_mb__before_clear_bit() barrier()
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#define smp_mb__after_clear_bit() barrier()
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static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
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static inline void clear_bit(int nr, volatile unsigned long *addr)
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{
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int *a = (int *)addr;
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int mask;
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@ -61,17 +107,7 @@ static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
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local_irq_restore(flags);
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}
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static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
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{
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int *a = (int *)addr;
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int mask;
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a += nr >> 5;
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mask = 1 << (nr & 0x1f);
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*a &= ~mask;
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}
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static __inline__ void change_bit(int nr, volatile unsigned long *addr)
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static inline void change_bit(int nr, volatile unsigned long *addr)
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{
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int mask, flags;
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unsigned long *ADDR = (unsigned long *)addr;
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@ -83,17 +119,7 @@ static __inline__ void change_bit(int nr, volatile unsigned long *addr)
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local_irq_restore(flags);
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}
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static __inline__ void __change_bit(int nr, volatile unsigned long *addr)
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{
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int mask;
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unsigned long *ADDR = (unsigned long *)addr;
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ADDR += nr >> 5;
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mask = 1 << (nr & 31);
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*ADDR ^= mask;
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}
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static __inline__ int test_and_set_bit(int nr, void *addr)
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static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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int mask, retval;
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volatile unsigned int *a = (volatile unsigned int *)addr;
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@ -109,19 +135,7 @@ static __inline__ int test_and_set_bit(int nr, void *addr)
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return retval;
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}
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static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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int mask, retval;
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volatile unsigned int *a = (volatile unsigned int *)addr;
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a += nr >> 5;
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mask = 1 << (nr & 0x1f);
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retval = (mask & *a) != 0;
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*a |= mask;
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return retval;
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}
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static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr)
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static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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int mask, retval;
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volatile unsigned int *a = (volatile unsigned int *)addr;
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@ -137,19 +151,7 @@ static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr)
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return retval;
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}
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static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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int mask, retval;
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volatile unsigned int *a = (volatile unsigned int *)addr;
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a += nr >> 5;
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mask = 1 << (nr & 0x1f);
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retval = (mask & *a) != 0;
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*a &= ~mask;
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return retval;
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}
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static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr)
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static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
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{
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int mask, retval;
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volatile unsigned int *a = (volatile unsigned int *)addr;
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@ -164,7 +166,69 @@ static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr)
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return retval;
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}
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static __inline__ int __test_and_change_bit(int nr,
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#endif /* CONFIG_SMP */
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/*
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* clear_bit() doesn't provide any barrier for the compiler.
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*/
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#define smp_mb__before_clear_bit() barrier()
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#define smp_mb__after_clear_bit() barrier()
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static inline void __set_bit(int nr, volatile unsigned long *addr)
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{
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int *a = (int *)addr;
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int mask;
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a += nr >> 5;
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mask = 1 << (nr & 0x1f);
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*a |= mask;
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}
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static inline void __clear_bit(int nr, volatile unsigned long *addr)
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{
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int *a = (int *)addr;
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int mask;
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a += nr >> 5;
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mask = 1 << (nr & 0x1f);
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*a &= ~mask;
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}
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static inline void __change_bit(int nr, volatile unsigned long *addr)
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{
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int mask;
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unsigned long *ADDR = (unsigned long *)addr;
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ADDR += nr >> 5;
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mask = 1 << (nr & 31);
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*ADDR ^= mask;
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}
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static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
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{
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int mask, retval;
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volatile unsigned int *a = (volatile unsigned int *)addr;
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a += nr >> 5;
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mask = 1 << (nr & 0x1f);
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retval = (mask & *a) != 0;
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*a |= mask;
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return retval;
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}
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static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
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{
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int mask, retval;
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volatile unsigned int *a = (volatile unsigned int *)addr;
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a += nr >> 5;
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mask = 1 << (nr & 0x1f);
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retval = (mask & *a) != 0;
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*a &= ~mask;
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return retval;
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}
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static inline int __test_and_change_bit(int nr,
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volatile unsigned long *addr)
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{
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int mask, retval;
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@ -177,16 +241,7 @@ static __inline__ int __test_and_change_bit(int nr,
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return retval;
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}
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/*
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* This routine doesn't need to be atomic.
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*/
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static __inline__ int __constant_test_bit(int nr, const void *addr)
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{
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return ((1UL << (nr & 31)) &
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(((const volatile unsigned int *)addr)[nr >> 5])) != 0;
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}
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static __inline__ int __test_bit(int nr, const void *addr)
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static inline int __test_bit(int nr, const void *addr)
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{
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int *a = (int *)addr;
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int mask;
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@ -196,10 +251,16 @@ static __inline__ int __test_bit(int nr, const void *addr)
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return ((mask & *a) != 0);
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}
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#define test_bit(nr,addr) \
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(__builtin_constant_p(nr) ? \
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__constant_test_bit((nr),(addr)) : \
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__test_bit((nr),(addr)))
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#ifndef CONFIG_SMP
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/*
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* This routine doesn't need irq save and restore ops in UP
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* context.
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*/
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static inline int test_bit(int nr, const void *addr)
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{
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return __test_bit(nr, addr);
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}
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#endif
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#include <asm-generic/bitops/find.h>
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#include <asm-generic/bitops/hweight.h>
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