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tg3: Revert PCIe tx glitch fix

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This patch reverts commit 52cdf8526f,
entitled "tg3: Prevent a PCIe tx glitch".  The problem does not have
any visible side-effects and happens too early for the driver to do
anything about it.  The proper place for this code is within the
device's bootcode.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
2010-07-11 09:31:45 +00:00
committed by David S. Miller
parent 6867c84381
commit 702e52ccd3
2 changed files with 0 additions and 46 deletions
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22
drivers/net/tg3.h
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@@ -2032,31 +2032,9 @@
/* Currently this is fixed. */
#define TG3_PHY_PCIE_ADDR 0x00
#define TG3_PHY_MII_ADDR 0x01
/*** Tigon3 specific PHY PCIE registers. ***/
#define TG3_PCIEPHY_BLOCK_ADDR 0x1f
#define TG3_PCIEPHY_XGXS_BLK1 0x0801
#define TG3_PCIEPHY_TXB_BLK 0x0861
#define TG3_PCIEPHY_BLOCK_SHIFT 4
/* TG3_PCIEPHY_TXB_BLK */
#define TG3_PCIEPHY_TX0CTRL1 0x15
#define TG3_PCIEPHY_TX0CTRL1_TXOCM 0x0003
#define TG3_PCIEPHY_TX0CTRL1_RDCTL 0x0008
#define TG3_PCIEPHY_TX0CTRL1_TXCMV 0x0030
#define TG3_PCIEPHY_TX0CTRL1_TKSEL 0x0040
#define TG3_PCIEPHY_TX0CTRL1_NB_EN 0x0400
/* TG3_PCIEPHY_XGXS_BLK1 */
#define TG3_PCIEPHY_PWRMGMT4 0x1a
#define TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN 0x0038
#define TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN 0x4000
/*** Tigon3 specific PHY MII registers. ***/
#define TG3_BMCR_SPEED1000 0x0040