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drm/nouveau: replace nv04_graph_fifo_access() use with direct reg bashing

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Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
2011-07-20 11:04:46 +10:00
parent 12a30e267c
commit 70ad25ab73
4 changed files with 8 additions and 20 deletions
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1
drivers/gpu/drm/nouveau/nouveau_drv.h
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@@ -1142,7 +1142,6 @@ extern int nvc0_fifo_unload_context(struct drm_device *);
/* nv04_graph.c */ /* nv04_graph.c */
extern int nv04_graph_create(struct drm_device *); extern int nv04_graph_create(struct drm_device *);
extern void nv04_graph_fifo_access(struct drm_device *, bool);
extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
u32 class, u32 mthd, u32 data); u32 class, u32 mthd, u32 data);

15
drivers/gpu/drm/nouveau/nv04_graph.c
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@@ -450,13 +450,13 @@ nv04_graph_context_del(struct nouveau_channel *chan, int engine)
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&dev_priv->context_switch_lock, flags); spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
nv04_graph_fifo_access(dev, false); nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
/* Unload the context if it's the currently active one */ /* Unload the context if it's the currently active one */
if (nv04_graph_channel(dev) == chan) if (nv04_graph_channel(dev) == chan)
nv04_graph_unload_context(dev); nv04_graph_unload_context(dev);
nv04_graph_fifo_access(dev, true); nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
/* Free the context resources */ /* Free the context resources */
@@ -545,17 +545,6 @@ nv04_graph_fini(struct drm_device *dev, int engine)
return 0; return 0;
} }
void
nv04_graph_fifo_access(struct drm_device *dev, bool enabled)
{
if (enabled)
nv_wr32(dev, NV04_PGRAPH_FIFO,
nv_rd32(dev, NV04_PGRAPH_FIFO) | 1);
else
nv_wr32(dev, NV04_PGRAPH_FIFO,
nv_rd32(dev, NV04_PGRAPH_FIFO) & ~1);
}
static int static int
nv04_graph_mthd_set_ref(struct nouveau_channel *chan, nv04_graph_mthd_set_ref(struct nouveau_channel *chan,
u32 class, u32 mthd, u32 data) u32 class, u32 mthd, u32 data)

8
drivers/gpu/drm/nouveau/nv10_graph.c
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@@ -708,8 +708,8 @@ static void nv10_graph_load_dma_vtxbuf(struct nouveau_channel *chan,
0x2c000000 | chan->id << 20 | subchan << 16 | 0x18c); 0x2c000000 | chan->id << 20 | subchan << 16 | 0x18c);
nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2_DL, inst); nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2_DL, inst);
nv_mask(dev, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000); nv_mask(dev, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000);
nv04_graph_fifo_access(dev, true); nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
nv04_graph_fifo_access(dev, false); nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
/* Restore the FIFO state */ /* Restore the FIFO state */
for (i = 0; i < ARRAY_SIZE(fifo); i++) for (i = 0; i < ARRAY_SIZE(fifo); i++)
@@ -879,13 +879,13 @@ nv10_graph_context_del(struct nouveau_channel *chan, int engine)
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&dev_priv->context_switch_lock, flags); spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
nv04_graph_fifo_access(dev, false); nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
/* Unload the context if it's the currently active one */ /* Unload the context if it's the currently active one */
if (nv10_graph_channel(dev) == chan) if (nv10_graph_channel(dev) == chan)
nv10_graph_unload_context(dev); nv10_graph_unload_context(dev);
nv04_graph_fifo_access(dev, true); nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
/* Free the context resources */ /* Free the context resources */

4
drivers/gpu/drm/nouveau/nv20_graph.c
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@@ -454,13 +454,13 @@ nv20_graph_context_del(struct nouveau_channel *chan, int engine)
unsigned long flags; unsigned long flags;
spin_lock_irqsave(&dev_priv->context_switch_lock, flags); spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
nv04_graph_fifo_access(dev, false); nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000);
/* Unload the context if it's the currently active one */ /* Unload the context if it's the currently active one */
if (nv10_graph_channel(dev) == chan) if (nv10_graph_channel(dev) == chan)
nv20_graph_unload_context(dev); nv20_graph_unload_context(dev);
nv04_graph_fifo_access(dev, true); nv_mask(dev, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
/* Free the context resources */ /* Free the context resources */