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KVM: x86 emulator: whitespace cleanups

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Clean up lines longer than 80 columns.  No code changes.

Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity
2011-04-20 13:12:27 +03:00
parent 3d9b938eef
commit 7295261cdd
1 changed files with 54 additions and 42 deletions
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96
arch/x86/kvm/emulate.c
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@@ -262,42 +262,42 @@ struct gprefix {
"w", "r", _LO32, "r", "", "r") "w", "r", _LO32, "r", "", "r")
/* Instruction has three operands and one operand is stored in ECX register */ /* Instruction has three operands and one operand is stored in ECX register */
#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \ #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
do { \ do { \
unsigned long _tmp; \ unsigned long _tmp; \
_type _clv = (_cl).val; \ _type _clv = (_cl).val; \
_type _srcv = (_src).val; \ _type _srcv = (_src).val; \
_type _dstv = (_dst).val; \ _type _dstv = (_dst).val; \
\ \
__asm__ __volatile__ ( \ __asm__ __volatile__ ( \
_PRE_EFLAGS("0", "5", "2") \ _PRE_EFLAGS("0", "5", "2") \
_op _suffix " %4,%1 \n" \ _op _suffix " %4,%1 \n" \
_POST_EFLAGS("0", "5", "2") \ _POST_EFLAGS("0", "5", "2") \
: "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \ : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
: "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \ : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
); \ ); \
\ \
(_cl).val = (unsigned long) _clv; \ (_cl).val = (unsigned long) _clv; \
(_src).val = (unsigned long) _srcv; \ (_src).val = (unsigned long) _srcv; \
(_dst).val = (unsigned long) _dstv; \ (_dst).val = (unsigned long) _dstv; \
} while (0) } while (0)
#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \ #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
do { \ do { \
switch ((_dst).bytes) { \ switch ((_dst).bytes) { \
case 2: \ case 2: \
__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
"w", unsigned short); \ "w", unsigned short); \
break; \ break; \
case 4: \ case 4: \
__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
"l", unsigned int); \ "l", unsigned int); \
break; \ break; \
case 8: \ case 8: \
ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \ ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
"q", unsigned long)); \ "q", unsigned long)); \
break; \ break; \
} \ } \
} while (0) } while (0)
#define __emulate_1op(_op, _dst, _eflags, _suffix) \ #define __emulate_1op(_op, _dst, _eflags, _suffix) \
@@ -360,13 +360,25 @@ struct gprefix {
} while (0) } while (0)
/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */ /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \ #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
do { \ do { \
switch((_src).bytes) { \ switch((_src).bytes) { \
case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \ case 1: \
case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \ __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \ _eflags, "b"); \
case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \ break; \
case 2: \
__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
_eflags, "w"); \
break; \
case 4: \
__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
_eflags, "l"); \
break; \
case 8: \
ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
_eflags, "q")); \
break; \
} \ } \
} while (0) } while (0)
@@ -402,7 +414,7 @@ struct gprefix {
(_type)_x; \ (_type)_x; \
}) })
#define insn_fetch_arr(_arr, _size, _eip) \ #define insn_fetch_arr(_arr, _size, _eip) \
({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \ ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
if (rc != X86EMUL_CONTINUE) \ if (rc != X86EMUL_CONTINUE) \
goto done; \ goto done; \