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sh: Support for L2 cache on newer SH-4A CPUs.

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This implements preliminary support for the L2 caches found
on newer SH-4A CPUs.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
2006-09-27 18:27:43 +09:00
parent 9d549a7d8e
commit 72c35543f8
4 changed files with 57 additions and 6 deletions
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9
include/asm-sh/processor.h
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@@ -54,14 +54,15 @@ enum cpu_type {
};
struct sh_cpuinfo {
enum cpu_type type;
unsigned int type;
unsigned long loops_per_jiffy;
struct cache_info icache;
struct cache_info dcache;
struct cache_info icache; /* Primary I-cache */
struct cache_info dcache; /* Primary D-cache */
struct cache_info scache; /* Secondary cache */
unsigned long flags;
};
} __attribute__ ((aligned(SMP_CACHE_BYTES)));
extern struct sh_cpuinfo boot_cpu_data;