Merge tag 'iommu-fixes-v3.7-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU fixes from Joerg Roedel: "Two fixes this time: 1. Another fix for a broken BIOS to detect when AMD IOMMU interrupt remapping can not work reliably 2. Typo fix for NVidia IOMMU driver" * tag 'iommu-fixes-v3.7-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: iommu/tegra: smmu: Fix deadly typo iommu/amd: Work around wrong IOAPIC device-id in IVRS table
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@@ -1599,21 +1599,46 @@ static void __init free_on_init_error(void)
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#endif
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#endif
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}
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}
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/* SB IOAPIC is always on this device in AMD systems */
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#define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
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static bool __init check_ioapic_information(void)
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static bool __init check_ioapic_information(void)
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{
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{
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bool ret, has_sb_ioapic;
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int idx;
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int idx;
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has_sb_ioapic = false;
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ret = false;
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for (idx = 0; idx < nr_ioapics; idx++) {
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for (idx = 0; idx < nr_ioapics; idx++) {
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int id = mpc_ioapic_id(idx);
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int devid, id = mpc_ioapic_id(idx);
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if (get_ioapic_devid(id) < 0) {
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devid = get_ioapic_devid(id);
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pr_err(FW_BUG "AMD-Vi: IO-APIC[%d] not in IVRS table\n", id);
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if (devid < 0) {
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pr_err("AMD-Vi: Disabling interrupt remapping due to BIOS Bug\n");
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pr_err(FW_BUG "AMD-Vi: IOAPIC[%d] not in IVRS table\n", id);
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return false;
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ret = false;
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} else if (devid == IOAPIC_SB_DEVID) {
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has_sb_ioapic = true;
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ret = true;
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}
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}
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}
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}
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return true;
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if (!has_sb_ioapic) {
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/*
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* We expect the SB IOAPIC to be listed in the IVRS
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* table. The system timer is connected to the SB IOAPIC
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* and if we don't have it in the list the system will
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* panic at boot time. This situation usually happens
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* when the BIOS is buggy and provides us the wrong
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* device id for the IOAPIC in the system.
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*/
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pr_err(FW_BUG "AMD-Vi: No southbridge IOAPIC found in IVRS table\n");
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}
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if (!ret)
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pr_err("AMD-Vi: Disabling interrupt remapping due to BIOS Bug(s)\n");
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return ret;
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}
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}
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static void __init free_dma_resources(void)
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static void __init free_dma_resources(void)
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@@ -200,7 +200,7 @@ enum {
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#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
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#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12)
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#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
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#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22)
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#define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22)
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#define SMMU_PDN_TO_ADDR(pdn) ((pdn) << 22)
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#define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
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#define _READABLE (1 << SMMU_PTB_DATA_ASID_READABLE_SHIFT)
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#define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
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#define _WRITABLE (1 << SMMU_PTB_DATA_ASID_WRITABLE_SHIFT)
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