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Merge tag 'microblaze-3.14-rc3' of git://git.monstr.eu/linux-2.6-microblaze

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Pull microblaze fixes from Michal Simek:
 - Fix two compilation issues - HZ, readq/writeq
 - Fix stack protection support

* tag 'microblaze-3.14-rc3' of git://git.monstr.eu/linux-2.6-microblaze:
  microblaze: Fix a typo when disabling stack protection
  microblaze: Define readq and writeq IO helper function
  microblaze: Fix missing HZ macro
This commit is contained in:
Linus Torvalds
2014-02-11 12:24:35 -08:00
parent a87af778d8 a49f56eec5
commit 738b52bb98
3 changed files with 9 additions and 1 deletions
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2
arch/microblaze/include/asm/delay.h
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@@ -13,6 +13,8 @@
#ifndef _ASM_MICROBLAZE_DELAY_H #ifndef _ASM_MICROBLAZE_DELAY_H
#define _ASM_MICROBLAZE_DELAY_H #define _ASM_MICROBLAZE_DELAY_H
#include <linux/param.h>
extern inline void __delay(unsigned long loops) extern inline void __delay(unsigned long loops)
{ {
asm volatile ("# __delay \n\t" \ asm volatile ("# __delay \n\t" \

6
arch/microblaze/include/asm/io.h
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@@ -89,6 +89,11 @@ static inline unsigned int readl(const volatile void __iomem *addr)
{ {
return le32_to_cpu(*(volatile unsigned int __force *)addr); return le32_to_cpu(*(volatile unsigned int __force *)addr);
} }
#define readq readq
static inline u64 readq(const volatile void __iomem *addr)
{
return le64_to_cpu(__raw_readq(addr));
}
static inline void writeb(unsigned char v, volatile void __iomem *addr) static inline void writeb(unsigned char v, volatile void __iomem *addr)
{ {
*(volatile unsigned char __force *)addr = v; *(volatile unsigned char __force *)addr = v;
@@ -101,6 +106,7 @@ static inline void writel(unsigned int v, volatile void __iomem *addr)
{ {
*(volatile unsigned int __force *)addr = cpu_to_le32(v); *(volatile unsigned int __force *)addr = cpu_to_le32(v);
} }
#define writeq(b, addr) __raw_writeq(cpu_to_le64(b), addr)
/* ioread and iowrite variants. thease are for now same as __raw_ /* ioread and iowrite variants. thease are for now same as __raw_
* variants of accessors. we might check for endianess in the feature * variants of accessors. we might check for endianess in the feature

2
arch/microblaze/kernel/head.S
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@@ -66,7 +66,7 @@ real_start:
mts rmsr, r0 mts rmsr, r0
/* Disable stack protection from bootloader */ /* Disable stack protection from bootloader */
mts rslr, r0 mts rslr, r0
addi r8, r0, 0xFFFFFFF addi r8, r0, 0xFFFFFFFF
mts rshr, r8 mts rshr, r8
/* /*
* According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc' * According to Xilinx, msrclr instruction behaves like 'mfs rX,rpc'