[MIPS] Routerboard 532: Support for base system
Signed-off-by: Phil Sutter <n0-1@freewrt.org> Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
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arch/mips/rb532/gpio.c
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arch/mips/rb532/gpio.c
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/*
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* Miscellaneous functions for IDT EB434 board
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*
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* Copyright 2004 IDT Inc. (rischelp@idt.com)
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* Copyright 2006 Phil Sutter <n0-1@freewrt.org>
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* Copyright 2007 Florian Fainelli <florian@openwrt.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/kernel.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <asm/addrspace.h>
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#include <asm/mach-rc32434/rb.h>
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struct rb532_gpio_reg __iomem *rb532_gpio_reg0;
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EXPORT_SYMBOL(rb532_gpio_reg0);
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struct mpmc_device dev3;
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static struct resource rb532_gpio_reg0_res[] = {
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{
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.name = "gpio_reg0",
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.start = (u32)(IDT434_REG_BASE + GPIOBASE),
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.end = (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)),
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.flags = IORESOURCE_MEM,
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}
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};
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static struct resource rb532_dev3_ctl_res[] = {
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{
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.name = "dev3_ctl",
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.start = (u32)(IDT434_REG_BASE + DEV3BASE),
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.end = (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)),
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.flags = IORESOURCE_MEM,
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}
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};
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void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val)
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{
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unsigned flags, data;
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unsigned i = 0;
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spin_lock_irqsave(&dev3.lock, flags);
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data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs);
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for (i = 0; i != len; ++i) {
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if (val & (1 << i))
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data |= (1 << (i + bit));
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else
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data &= ~(1 << (i + bit));
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}
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writel(data, (IDT434_REG_BASE + reg_offs));
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spin_unlock_irqrestore(&dev3.lock, flags);
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}
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EXPORT_SYMBOL(set_434_reg);
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unsigned get_434_reg(unsigned reg_offs)
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{
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return readl(IDT434_REG_BASE + reg_offs);
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}
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EXPORT_SYMBOL(get_434_reg);
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void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
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{
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unsigned flags;
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spin_lock_irqsave(&dev3.lock, flags);
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dev3.state = (dev3.state | or_mask) & ~nand_mask;
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writel(dev3.state, &dev3.base);
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spin_unlock_irqrestore(&dev3.lock, flags);
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}
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EXPORT_SYMBOL(set_latch_u5);
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unsigned char get_latch_u5(void)
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{
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return dev3.state;
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}
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EXPORT_SYMBOL(get_latch_u5);
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int rb532_gpio_get_value(unsigned gpio)
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{
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return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio);
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}
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EXPORT_SYMBOL(rb532_gpio_get_value);
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void rb532_gpio_set_value(unsigned gpio, int value)
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{
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unsigned tmp;
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tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio);
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if (value)
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tmp |= 1 << gpio;
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writel(tmp, (void *)&rb532_gpio_reg0->gpiod);
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}
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EXPORT_SYMBOL(rb532_gpio_set_value);
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int rb532_gpio_direction_input(unsigned gpio)
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{
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writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio),
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(void *)&rb532_gpio_reg0->gpiocfg);
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return 0;
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}
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EXPORT_SYMBOL(rb532_gpio_direction_input);
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int rb532_gpio_direction_output(unsigned gpio, int value)
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{
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gpio_set_value(gpio, value);
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writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio),
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(void *)&rb532_gpio_reg0->gpiocfg);
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return 0;
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}
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EXPORT_SYMBOL(rb532_gpio_direction_output);
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void rb532_gpio_set_int_level(unsigned gpio, int value)
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{
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unsigned tmp;
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tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio);
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if (value)
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tmp |= 1 << gpio;
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writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel);
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}
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EXPORT_SYMBOL(rb532_gpio_set_int_level);
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int rb532_gpio_get_int_level(unsigned gpio)
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{
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return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio);
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}
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EXPORT_SYMBOL(rb532_gpio_get_int_level);
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void rb532_gpio_set_int_status(unsigned gpio, int value)
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{
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unsigned tmp;
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tmp = readl(&rb532_gpio_reg0->gpioistat);
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if (value)
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tmp |= 1 << gpio;
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writel(tmp, (void *)&rb532_gpio_reg0->gpioistat);
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}
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EXPORT_SYMBOL(rb532_gpio_set_int_status);
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int rb532_gpio_get_int_status(unsigned gpio)
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{
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return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio);
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}
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EXPORT_SYMBOL(rb532_gpio_get_int_status);
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void rb532_gpio_set_func(unsigned gpio, int value)
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{
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unsigned tmp;
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tmp = readl(&rb532_gpio_reg0->gpiofunc);
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if (value)
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tmp |= 1 << gpio;
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writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc);
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}
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EXPORT_SYMBOL(rb532_gpio_set_func);
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int rb532_gpio_get_func(unsigned gpio)
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{
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return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio);
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}
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EXPORT_SYMBOL(rb532_gpio_get_func);
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int __init rb532_gpio_init(void)
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{
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rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start,
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rb532_gpio_reg0_res[0].end -
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rb532_gpio_reg0_res[0].start);
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if (!rb532_gpio_reg0) {
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printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
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return -ENXIO;
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}
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dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start,
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rb532_dev3_ctl_res[0].end -
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rb532_dev3_ctl_res[0].start);
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if (!dev3.base) {
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printk(KERN_ERR "rb532: cannot remap device controller 3\n");
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return -ENXIO;
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}
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return 0;
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}
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arch_initcall(rb532_gpio_init);
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