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Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6

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* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (47 commits)
  OMAP clock: use debugfs_remove_recursive() for rewinding
  OMAP2/3/4 core: create omap_device layer
  OMAP: omap_hwmod: call omap_hwmod init at boot; create interconnects
  OMAP2/3/4: create omap_hwmod layer
  OMAP2/3 board-*.c files: read bootloader configuration earlier
  OMAP2/3/4 PRCM: add module IDLEST wait code
  OMAP2/3 PM: create the OMAP PM interface and add a default OMAP PM no-op layer
  OMAP3 clock: remove superfluous calls to omap2_init_clk_clkdm
  OMAP clock: associate MPU clocks with the mpu_clkdm
  OMAP3 clock: Fixed processing of bootarg 'mpurate'
  OMAP: SDRC: Add several new register definitions
  OMAP: powerdomain: Fix overflow when doing powerdomain deps lookups.
  OMAP: PM: Added suspend target state control to debugfs for OMAP3
  OMAP: PM debug: Add PRCM register dump support
  OMAP: PM debug: make powerdomains use PM-debug counters
  OMAP: PM: Add pm-debug counters
  OMAP: PM: Add closures to clkdm_for_each and pwrdm_for_each.
  OMAP: PM: Hook into PM counters
  OMAP: PM counter infrastructure.
  OMAP3: PM: fix lockdep warning caused by omap3_pm_init
  ...
This commit is contained in:
Linus Torvalds
2009-09-18 09:19:26 -07:00
parent 5ce0028987 1f685b36db
commit 73c583e4e2
103 changed files with 7776 additions and 718 deletions
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115
arch/arm/plat-omap/gpio.c
View File

@@ -31,7 +31,7 @@
/*
* OMAP1510 GPIO registers
*/
#define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
#define OMAP1510_GPIO_BASE OMAP1_IO_ADDRESS(0xfffce000)
#define OMAP1510_GPIO_DATA_INPUT 0x00
#define OMAP1510_GPIO_DATA_OUTPUT 0x04
#define OMAP1510_GPIO_DIR_CONTROL 0x08
@@ -45,10 +45,10 @@
/*
* OMAP1610 specific GPIO registers
*/
#define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
#define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
#define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
#define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
#define OMAP1610_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbe400)
#define OMAP1610_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbec00)
#define OMAP1610_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbb400)
#define OMAP1610_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbbc00)
#define OMAP1610_GPIO_REVISION 0x0000
#define OMAP1610_GPIO_SYSCONFIG 0x0010
#define OMAP1610_GPIO_SYSSTATUS 0x0014
@@ -70,12 +70,12 @@
/*
* OMAP730 specific GPIO registers
*/
#define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
#define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
#define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
#define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
#define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
#define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
#define OMAP730_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
#define OMAP730_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
#define OMAP730_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
#define OMAP730_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
#define OMAP730_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
#define OMAP730_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
#define OMAP730_GPIO_DATA_INPUT 0x00
#define OMAP730_GPIO_DATA_OUTPUT 0x04
#define OMAP730_GPIO_DIR_CONTROL 0x08
@@ -86,12 +86,12 @@
/*
* OMAP850 specific GPIO registers
*/
#define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000)
#define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800)
#define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000)
#define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800)
#define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000)
#define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800)
#define OMAP850_GPIO1_BASE OMAP1_IO_ADDRESS(0xfffbc000)
#define OMAP850_GPIO2_BASE OMAP1_IO_ADDRESS(0xfffbc800)
#define OMAP850_GPIO3_BASE OMAP1_IO_ADDRESS(0xfffbd000)
#define OMAP850_GPIO4_BASE OMAP1_IO_ADDRESS(0xfffbd800)
#define OMAP850_GPIO5_BASE OMAP1_IO_ADDRESS(0xfffbe000)
#define OMAP850_GPIO6_BASE OMAP1_IO_ADDRESS(0xfffbe800)
#define OMAP850_GPIO_DATA_INPUT 0x00
#define OMAP850_GPIO_DATA_OUTPUT 0x04
#define OMAP850_GPIO_DIR_CONTROL 0x08
@@ -99,19 +99,21 @@
#define OMAP850_GPIO_INT_MASK 0x10
#define OMAP850_GPIO_INT_STATUS 0x14
#define OMAP1_MPUIO_VBASE OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
/*
* omap24xx specific GPIO registers
*/
#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
#define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
#define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
#define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
#define OMAP242X_GPIO1_BASE OMAP2_IO_ADDRESS(0x48018000)
#define OMAP242X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4801a000)
#define OMAP242X_GPIO3_BASE OMAP2_IO_ADDRESS(0x4801c000)
#define OMAP242X_GPIO4_BASE OMAP2_IO_ADDRESS(0x4801e000)
#define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
#define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
#define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
#define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
#define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
#define OMAP243X_GPIO1_BASE OMAP2_IO_ADDRESS(0x4900C000)
#define OMAP243X_GPIO2_BASE OMAP2_IO_ADDRESS(0x4900E000)
#define OMAP243X_GPIO3_BASE OMAP2_IO_ADDRESS(0x49010000)
#define OMAP243X_GPIO4_BASE OMAP2_IO_ADDRESS(0x49012000)
#define OMAP243X_GPIO5_BASE OMAP2_IO_ADDRESS(0x480B6000)
#define OMAP24XX_GPIO_REVISION 0x0000
#define OMAP24XX_GPIO_SYSCONFIG 0x0010
@@ -168,24 +170,22 @@
* omap34xx specific GPIO registers
*/
#define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
#define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
#define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
#define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
#define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
#define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
#define OMAP34XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x48310000)
#define OMAP34XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x49050000)
#define OMAP34XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x49052000)
#define OMAP34XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x49054000)
#define OMAP34XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x49056000)
#define OMAP34XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x49058000)
/*
* OMAP44XX specific GPIO registers
*/
#define OMAP44XX_GPIO1_BASE IO_ADDRESS(0x4a310000)
#define OMAP44XX_GPIO2_BASE IO_ADDRESS(0x48055000)
#define OMAP44XX_GPIO3_BASE IO_ADDRESS(0x48057000)
#define OMAP44XX_GPIO4_BASE IO_ADDRESS(0x48059000)
#define OMAP44XX_GPIO5_BASE IO_ADDRESS(0x4805B000)
#define OMAP44XX_GPIO6_BASE IO_ADDRESS(0x4805D000)
#define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
#define OMAP44XX_GPIO1_BASE OMAP2_IO_ADDRESS(0x4a310000)
#define OMAP44XX_GPIO2_BASE OMAP2_IO_ADDRESS(0x48055000)
#define OMAP44XX_GPIO3_BASE OMAP2_IO_ADDRESS(0x48057000)
#define OMAP44XX_GPIO4_BASE OMAP2_IO_ADDRESS(0x48059000)
#define OMAP44XX_GPIO5_BASE OMAP2_IO_ADDRESS(0x4805B000)
#define OMAP44XX_GPIO6_BASE OMAP2_IO_ADDRESS(0x4805D000)
struct gpio_bank {
void __iomem *base;
@@ -221,7 +221,7 @@ struct gpio_bank {
#ifdef CONFIG_ARCH_OMAP16XX
static struct gpio_bank gpio_bank_1610[5] = {
{ OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
{ OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
{ OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
{ OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
{ OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
@@ -231,14 +231,14 @@ static struct gpio_bank gpio_bank_1610[5] = {
#ifdef CONFIG_ARCH_OMAP15XX
static struct gpio_bank gpio_bank_1510[2] = {
{ OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
{ OMAP1_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
{ OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
};
#endif
#ifdef CONFIG_ARCH_OMAP730
static struct gpio_bank gpio_bank_730[7] = {
{ OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
{ OMAP1_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
{ OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
{ OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
{ OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
@@ -250,7 +250,7 @@ static struct gpio_bank gpio_bank_730[7] = {
#ifdef CONFIG_ARCH_OMAP850
static struct gpio_bank gpio_bank_850[7] = {
{ OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
{ OMAP1_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
{ OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
{ OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
{ OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
@@ -2032,7 +2032,7 @@ void omap2_gpio_resume_after_retention(void)
return;
for (i = 0; i < gpio_bank_count; i++) {
struct gpio_bank *bank = &gpio_bank[i];
u32 l;
u32 l, gen, gen0, gen1;
if (!(bank->enabled_non_wakeup_gpios))
continue;
@@ -2056,13 +2056,32 @@ void omap2_gpio_resume_after_retention(void)
* this silicon bug. */
l ^= bank->saved_datain;
l &= bank->non_wakeup_gpios;
if (l) {
/*
* No need to generate IRQs for the rising edge for gpio IRQs
* configured with falling edge only; and vice versa.
*/
gen0 = l & bank->saved_fallingdetect;
gen0 &= bank->saved_datain;
gen1 = l & bank->saved_risingdetect;
gen1 &= ~(bank->saved_datain);
/* FIXME: Consider GPIO IRQs with level detections properly! */
gen = l & (~(bank->saved_fallingdetect) &
~(bank->saved_risingdetect));
/* Consider all GPIO IRQs needed to be updated */
gen |= gen0 | gen1;
if (gen) {
u32 old0, old1;
#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
__raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
__raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
__raw_writel(old0 | gen, bank->base +
OMAP24XX_GPIO_LEVELDETECT0);
__raw_writel(old1 | gen, bank->base +
OMAP24XX_GPIO_LEVELDETECT1);
__raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
__raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
#endif