MIPS: Alchemy: Redo PCI as platform driver
- Rewrite Alchemy PCI support as a platform driver. - Fixup boards which have PCI. Run-tested on DB1500 and DB1550. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2706/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/alchemy/common/pci.c delete mode 100644 arch/mips/pci/fixup-au1000.c delete mode 100644 arch/mips/pci/ops-au1000.c create mode 100644 arch/mips/pci/pci-alchemy.c
This commit is contained in:
Manuel Lauss
committed by
Ralf Baechle
Ralf Baechle
parent
7cc2e272da
commit
7517de3486
@@ -254,6 +254,14 @@ enum alchemy_usb_block {
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};
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int alchemy_usb_control(int block, int enable);
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/* PCI controller platform data */
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struct alchemy_pci_platdata {
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int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin);
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int (*board_pci_idsel)(unsigned int devsel, int assert);
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/* bits to set/clear in PCI_CONFIG register */
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unsigned long pci_cfg_set;
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unsigned long pci_cfg_clr;
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};
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/* SOC Interrupt numbers */
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@@ -1309,58 +1317,30 @@ enum soc_au1200_ints {
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# define AC97C_RS (1 << 1)
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# define AC97C_CE (1 << 0)
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#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
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/* Au1500 PCI Controller */
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#define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
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#define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
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#define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
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# define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
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(1 << 25) | (1 << 26) | (1 << 27))
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#define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
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#define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
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#define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
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#define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
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#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
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#define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
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#define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
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#define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
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#define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
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#define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
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#define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
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#define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
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#define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
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/*
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* All of our structures, like PCI resource, have 32-bit members.
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* Drivers are expected to do an ioremap on the PCI MEM resource, but it's
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* hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
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* to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
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* (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
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* addresses. For PCI I/O, it's simpler because we get to do the ioremap
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* ourselves and then adjust the device's resources.
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/* The PCI chip selects are outside the 32bit space, and since we can't
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* just program the 36bit addresses into BARs, we have to take a chunk
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* out of the 32bit space and reserve it for PCI. When these addresses
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* are ioremap()ed, they'll be fixed up to the real 36bit address before
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* being passed to the real ioremap function.
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*/
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#define Au1500_EXT_CFG 0x600000000ULL
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#define Au1500_EXT_CFG_TYPE1 0x680000000ULL
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#define Au1500_PCI_IO_START 0x500000000ULL
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#define Au1500_PCI_IO_END 0x5000FFFFFULL
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#define Au1500_PCI_MEM_START 0x440000000ULL
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#define Au1500_PCI_MEM_END 0x44FFFFFFFULL
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#define ALCHEMY_PCI_MEMWIN_START (AU1500_PCI_MEM_PHYS_ADDR >> 4)
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#define ALCHEMY_PCI_MEMWIN_END (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)
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#define PCI_IO_START 0x00001000
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#define PCI_IO_END 0x000FFFFF
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#define PCI_MEM_START 0x40000000
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#define PCI_MEM_END 0x4FFFFFFF
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/* for PCI IO it's simpler because we get to do the ioremap ourselves and then
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* adjust the device's resources.
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*/
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#define ALCHEMY_PCI_IOWIN_START 0x00001000
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#define ALCHEMY_PCI_IOWIN_END 0x0000FFFF
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#define PCI_FIRST_DEVFN (0 << 3)
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#define PCI_LAST_DEVFN (19 << 3)
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#ifdef CONFIG_PCI
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#define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
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#define IOPORT_RESOURCE_END 0xffffffff
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#define IOMEM_RESOURCE_START 0x10000000
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#define IOMEM_RESOURCE_END 0xfffffffffULL
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#else /* Au1000 and Au1100 and Au1200 */
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#else
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/* Don't allow any legacy ports probing */
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#define IOPORT_RESOURCE_START 0x10000000
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@@ -1368,13 +1348,77 @@ enum soc_au1200_ints {
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#define IOMEM_RESOURCE_START 0x10000000
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#define IOMEM_RESOURCE_END 0xfffffffffULL
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#define PCI_IO_START 0
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#define PCI_IO_END 0
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#define PCI_MEM_START 0
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#define PCI_MEM_END 0
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#define PCI_FIRST_DEVFN 0
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#define PCI_LAST_DEVFN 0
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#endif
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/* PCI controller block register offsets */
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#define PCI_REG_CMEM 0x0000
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#define PCI_REG_CONFIG 0x0004
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#define PCI_REG_B2BMASK_CCH 0x0008
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#define PCI_REG_B2BBASE0_VID 0x000C
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#define PCI_REG_B2BBASE1_SID 0x0010
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#define PCI_REG_MWMASK_DEV 0x0014
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#define PCI_REG_MWBASE_REV_CCL 0x0018
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#define PCI_REG_ERR_ADDR 0x001C
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#define PCI_REG_SPEC_INTACK 0x0020
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#define PCI_REG_ID 0x0100
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#define PCI_REG_STATCMD 0x0104
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#define PCI_REG_CLASSREV 0x0108
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#define PCI_REG_PARAM 0x010C
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#define PCI_REG_MBAR 0x0110
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#define PCI_REG_TIMEOUT 0x0140
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/* PCI controller block register bits */
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#define PCI_CMEM_E (1 << 28) /* enable cacheable memory */
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#define PCI_CMEM_CMBASE(x) (((x) & 0x3fff) << 14)
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#define PCI_CMEM_CMMASK(x) ((x) & 0x3fff)
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#define PCI_CONFIG_ERD (1 << 27) /* pci error during R/W */
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#define PCI_CONFIG_ET (1 << 26) /* error in target mode */
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#define PCI_CONFIG_EF (1 << 25) /* fatal error */
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#define PCI_CONFIG_EP (1 << 24) /* parity error */
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#define PCI_CONFIG_EM (1 << 23) /* multiple errors */
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#define PCI_CONFIG_BM (1 << 22) /* bad master error */
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#define PCI_CONFIG_PD (1 << 20) /* PCI Disable */
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#define PCI_CONFIG_BME (1 << 19) /* Byte Mask Enable for reads */
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#define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */
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#define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */
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#define PCI_CONFIG_IP (1 << 13) /* int on PCI_PERR# */
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#define PCI_CONFIG_IS (1 << 12) /* int on PCI_SERR# */
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#define PCI_CONFIG_IMM (1 << 11) /* int on master abort */
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#define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */
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#define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */
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#define PCI_CONFIG_IPB (1 << 8) /* int on PERR# in bus master acc */
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#define PCI_CONFIG_SIC_NO (0 << 6) /* no byte mask changes */
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#define PCI_CONFIG_SIC_BA_ADR (1 << 6) /* on byte/hw acc, invert adr bits */
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#define PCI_CONFIG_SIC_HWA_DAT (2 << 6) /* on halfword acc, swap data */
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#define PCI_CONFIG_SIC_ALL (3 << 6) /* swap data bytes on all accesses */
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#define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */
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#define PCI_CONFIG_SM (1 << 4) /* swap data from PCI ctl */
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#define PCI_CONFIG_AEN (1 << 3) /* enable internal arbiter */
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#define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */
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#define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */
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#define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */
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#define PCI_B2BMASK_B2BMASK(x) (((x) & 0xffff) << 16)
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#define PCI_B2BMASK_CCH(x) ((x) & 0xffff) /* 16 upper bits of class code */
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#define PCI_B2BBASE0_VID_B0(x) (((x) & 0xffff) << 16)
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#define PCI_B2BBASE0_VID_SV(x) ((x) & 0xffff)
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#define PCI_B2BBASE1_SID_B1(x) (((x) & 0xffff) << 16)
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#define PCI_B2BBASE1_SID_SI(x) ((x) & 0xffff)
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#define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
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#define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff)
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#define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)
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#define PCI_MWBASEREVCCL_REV(x) (((x) & 0xff) << 8)
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#define PCI_MWBASEREVCCL_CCL(x) ((x) & 0xff)
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#define PCI_ID_DID(x) (((x) & 0xffff) << 16)
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#define PCI_ID_VID(x) ((x) & 0xffff)
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#define PCI_STATCMD_STATUS(x) (((x) & 0xffff) << 16)
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#define PCI_STATCMD_CMD(x) ((x) & 0xffff)
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#define PCI_CLASSREV_CLASS(x) (((x) & 0x00ffffff) << 8)
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#define PCI_CLASSREV_REV(x) ((x) & 0xff)
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#define PCI_PARAM_BIST(x) (((x) & 0xff) << 24)
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#define PCI_PARAM_HT(x) (((x) & 0xff) << 16)
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#define PCI_PARAM_LT(x) (((x) & 0xff) << 8)
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#define PCI_PARAM_CLS(x) ((x) & 0xff)
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#define PCI_TIMEOUT_RETRIES(x) (((x) & 0xff) << 8) /* max retries */
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#define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */
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#endif
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