powerpc/fsl-booke: Use HW PTE format if CONFIG_PTE_64BIT
Switch to using the Power ISA defined PTE format when we have a 64-bit PTE. This makes the code handling between fsl-booke and book3e-64 similiar for TLB faults. Additionally this lets use take advantage of the page size encodings and full permissions that the HW PTE defines. Also defined _PMD_PRESENT, _PMD_PRESENT_MASK, and _PMD_BAD since the 32-bit ppc arch code expects them. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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committed by
Benjamin Herrenschmidt
parent
1d5d9527d8
commit
76acc2c1a7
@@ -111,6 +111,8 @@ extern int icache_44x_need_flush;
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#include <asm/pte-40x.h>
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#elif defined(CONFIG_44x)
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#include <asm/pte-44x.h>
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#elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
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#include <asm/pte-book3e.h>
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#elif defined(CONFIG_FSL_BOOKE)
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#include <asm/pte-fsl-booke.h>
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#elif defined(CONFIG_8xx)
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@@ -75,6 +75,9 @@
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/* On 32-bit, we never clear the top part of the PTE */
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#ifdef CONFIG_PPC32
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#define _PTE_NONE_MASK 0xffffffff00000000ULL
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#define _PMD_PRESENT 0
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#define _PMD_PRESENT_MASK (PAGE_MASK)
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#define _PMD_BAD (~PAGE_MASK)
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#endif
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#endif /* __KERNEL__ */
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@@ -33,13 +33,6 @@
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#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
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#define _PAGE_SPECIAL 0x00800 /* S: Special page */
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#ifdef CONFIG_PTE_64BIT
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/* ERPN in a PTE never gets cleared, ignore it */
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#define _PTE_NONE_MASK 0xffffffffffff0000ULL
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/* We extend the size of the PTE flags area when using 64-bit PTEs */
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#define PTE_RPN_SHIFT (PAGE_SHIFT + 8)
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#endif
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#define _PMD_PRESENT 0
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#define _PMD_PRESENT_MASK (PAGE_MASK)
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#define _PMD_BAD (~PAGE_MASK)
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