gpio: Add Intel Centerton support to gpio-sch
This patch adds the Intel Centerton processor device ID for GPIO. The device ID is defined in include/linux/pci_ids.h Signed-off-by: Seth Heasley <seth.heasley@intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
committed by
Samuel Ortiz
parent
1fe17a24e2
commit
77820ffae6
@@ -170,13 +170,13 @@ config GPIO_VR41XX
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Say yes here to support the NEC VR4100 series General-purpose I/O Uint
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Say yes here to support the NEC VR4100 series General-purpose I/O Uint
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config GPIO_SCH
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config GPIO_SCH
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tristate "Intel SCH/TunnelCreek GPIO"
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tristate "Intel SCH/TunnelCreek/Centerton GPIO"
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depends on PCI && X86
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depends on PCI && X86
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select MFD_CORE
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select MFD_CORE
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select LPC_SCH
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select LPC_SCH
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help
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help
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Say yes here to support GPIO interface on Intel Poulsbo SCH
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Say yes here to support GPIO interface on Intel Poulsbo SCH,
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or Intel Tunnel Creek processor.
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Intel Tunnel Creek processor or Intel Centerton processor.
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The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are
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The Intel SCH contains a total of 14 GPIO pins. Ten GPIOs are
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powered by the core power rail and are turned off during sleep
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powered by the core power rail and are turned off during sleep
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modes (S3 and higher). The remaining four GPIOs are powered by
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modes (S3 and higher). The remaining four GPIOs are powered by
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@@ -185,6 +185,9 @@ config GPIO_SCH
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system from the Suspend-to-RAM state.
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system from the Suspend-to-RAM state.
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The Intel Tunnel Creek processor has 5 GPIOs powered by the
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The Intel Tunnel Creek processor has 5 GPIOs powered by the
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core power rail and 9 from suspend power supply.
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core power rail and 9 from suspend power supply.
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The Intel Centerton processor has a total of 30 GPIO pins.
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Twenty-one are powered by the core power rail and 9 from the
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suspend power supply.
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config GPIO_ICH
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config GPIO_ICH
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tristate "Intel ICH GPIO"
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tristate "Intel ICH GPIO"
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@@ -232,6 +232,14 @@ static int __devinit sch_gpio_probe(struct platform_device *pdev)
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sch_gpio_resume.ngpio = 9;
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sch_gpio_resume.ngpio = 9;
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break;
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break;
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case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
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sch_gpio_core.base = 0;
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sch_gpio_core.ngpio = 21;
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sch_gpio_resume.base = 21;
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sch_gpio_resume.ngpio = 9;
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break;
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default:
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default:
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return -ENODEV;
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return -ENODEV;
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}
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}
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