From 7d896aaceb0ac361abf581b3b21de20f52da0ce9 Mon Sep 17 00:00:00 2001 From: Jonghwan Choi Date: Wed, 27 Jun 2012 09:47:35 +0900 Subject: [PATCH 1/5] ARM: EXYNOS: Clear SYS_WDTRESET bit to use watchdog reset When SYS_WDTRESET is set, watchdog timer reset request is ignored by power management unit. Signed-off-by: Jonghwan Choi Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/include/mach/regs-pmu.h | 5 +++++ arch/arm/mach-exynos/pmu.c | 14 ++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index 43a99e6f56ab..d4e392b811a3 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -232,6 +232,11 @@ #define EXYNOS5_USB_CFG S5P_PMUREG(0x0230) +#define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408) +#define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C) + +#define EXYNOS5_SYS_WDTRESET (1 << 20) + #define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index 4aacb66f7161..bb4c522f8e05 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -390,6 +390,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode) static int __init exynos_pmu_init(void) { + unsigned int value; + exynos_pmu_config = exynos4210_pmu_config; if (soc_is_exynos4210()) { @@ -399,6 +401,18 @@ static int __init exynos_pmu_init(void) exynos_pmu_config = exynos4x12_pmu_config; pr_info("EXYNOS4x12 PMU Initialize\n"); } else if (soc_is_exynos5250()) { + /* + * When SYS_WDTRESET is set, watchdog timer reset request + * is ignored by power management unit. + */ + value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE); + value &= ~EXYNOS5_SYS_WDTRESET; + __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE); + + value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST); + value &= ~EXYNOS5_SYS_WDTRESET; + __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); + exynos_pmu_config = exynos5250_pmu_config; pr_info("EXYNOS5250 PMU Initialize\n"); } else { From c4c713554407a4afa2c1cadcc0f10e199742a4bc Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Wed, 20 Jun 2012 16:34:25 +0900 Subject: [PATCH 2/5] ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12 Adds clock setting entries for EXYNOS4212 and EXYNOS4412 platforms. Signed-off-by: Sachin Kamat [fixed compilation warning which is reported by Arnd Bergmann] Signed-off-by: Kukjin Kim --- .../mach-exynos/include/mach/regs-usb-phy.h | 20 +++++-- arch/arm/mach-exynos/setup-usb-phy.c | 60 ++++++++++++++----- arch/arm/plat-samsung/include/plat/cpu.h | 4 ++ 3 files changed, 63 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h index c337cf3a71bf..07277735252e 100644 --- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h +++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h @@ -35,11 +35,21 @@ #define PHY1_COMMON_ON_N (1 << 7) #define PHY0_COMMON_ON_N (1 << 4) #define PHY0_ID_PULLUP (1 << 2) -#define CLKSEL_MASK (0x3 << 0) -#define CLKSEL_SHIFT (0) -#define CLKSEL_48M (0x0 << 0) -#define CLKSEL_12M (0x2 << 0) -#define CLKSEL_24M (0x3 << 0) + +#define EXYNOS4_CLKSEL_SHIFT (0) + +#define EXYNOS4210_CLKSEL_MASK (0x3 << 0) +#define EXYNOS4210_CLKSEL_48M (0x0 << 0) +#define EXYNOS4210_CLKSEL_12M (0x2 << 0) +#define EXYNOS4210_CLKSEL_24M (0x3 << 0) + +#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0) +#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0) +#define EXYNOS4X12_CLKSEL_10M (0x1 << 0) +#define EXYNOS4X12_CLKSEL_12M (0x2 << 0) +#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0) +#define EXYNOS4X12_CLKSEL_20M (0x4 << 0) +#define EXYNOS4X12_CLKSEL_24M (0x5 << 0) #define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08) #define HOST_LINK_PORT_SWRST_MASK (0xf << 6) diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c index 1af0a7f44e00..b81cc569a8dd 100644 --- a/arch/arm/mach-exynos/setup-usb-phy.c +++ b/arch/arm/mach-exynos/setup-usb-phy.c @@ -31,27 +31,55 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev) struct clk *xusbxti_clk; u32 phyclk; - /* set clock frequency for PLL */ - phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK; - xusbxti_clk = clk_get(&pdev->dev, "xusbxti"); if (xusbxti_clk && !IS_ERR(xusbxti_clk)) { - switch (clk_get_rate(xusbxti_clk)) { - case 12 * MHZ: - phyclk |= CLKSEL_12M; - break; - case 24 * MHZ: - phyclk |= CLKSEL_24M; - break; - default: - case 48 * MHZ: - /* default reference clock */ - break; + if (soc_is_exynos4210()) { + /* set clock frequency for PLL */ + phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK; + + switch (clk_get_rate(xusbxti_clk)) { + case 12 * MHZ: + phyclk |= EXYNOS4210_CLKSEL_12M; + break; + case 48 * MHZ: + phyclk |= EXYNOS4210_CLKSEL_48M; + break; + default: + case 24 * MHZ: + phyclk |= EXYNOS4210_CLKSEL_24M; + break; + } + writel(phyclk, EXYNOS4_PHYCLK); + } else if (soc_is_exynos4212() || soc_is_exynos4412()) { + /* set clock frequency for PLL */ + phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK; + + switch (clk_get_rate(xusbxti_clk)) { + case 9600 * KHZ: + phyclk |= EXYNOS4X12_CLKSEL_9600K; + break; + case 10 * MHZ: + phyclk |= EXYNOS4X12_CLKSEL_10M; + break; + case 12 * MHZ: + phyclk |= EXYNOS4X12_CLKSEL_12M; + break; + case 19200 * KHZ: + phyclk |= EXYNOS4X12_CLKSEL_19200K; + break; + case 20 * MHZ: + phyclk |= EXYNOS4X12_CLKSEL_20M; + break; + default: + case 24 * MHZ: + /* default reference clock */ + phyclk |= EXYNOS4X12_CLKSEL_24M; + break; + } + writel(phyclk, EXYNOS4_PHYCLK); } clk_put(xusbxti_clk); } - - writel(phyclk, EXYNOS4_PHYCLK); } static int exynos4210_usb_phy0_init(struct platform_device *pdev) diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 0721293fad63..ace4451b7651 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h @@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } +#ifndef KHZ +#define KHZ (1000) +#endif + #ifndef MHZ #define MHZ (1000*1000) #endif From 2a2b0e208ef57225cf0ce9b777749c11173483a1 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Jul 2012 16:34:51 +0900 Subject: [PATCH 3/5] ARM: EXYNOS: Make combiner_init function static Fixes the following warning: arch/arm/mach-exynos/common.c:543:13: warning: symbol 'combiner_init' was not declared. Should it be static? Signed-off-by: Sachin Kamat Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 742edd3bbec3..1b0922cda4ab 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -540,7 +540,8 @@ static struct irq_domain_ops combiner_irq_domain_ops = { .map = combiner_irq_domain_map, }; -void __init combiner_init(void __iomem *combiner_base, struct device_node *np) +static void __init combiner_init(void __iomem *combiner_base, + struct device_node *np) { int i, irq, irq_base; unsigned int max_nr, nr_irq; From 12f081ffeefbebac085dc6e2138cd06e4803d9a0 Mon Sep 17 00:00:00 2001 From: Sachin Kamat Date: Thu, 12 Jul 2012 16:49:10 +0900 Subject: [PATCH 4/5] ARM: EXYNOS: Add missing static storage class specifier in pmu.c file arch/arm/mach-exynos/pmu.c:318:14: warning: symbol 'exynos5_list_both_cnt_feed' was not declared. Should it be static? arch/arm/mach-exynos/pmu.c:332:14: warning: symbol 'exynos5_list_diable_wfi_wfe' was not declared. Should it be static? Signed-off-by: Sachin Kamat Signed-off-by: Kukjin Kim --- arch/arm/mach-exynos/pmu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index bb4c522f8e05..3a48c852be6c 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -315,7 +315,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = { { PMU_TABLE_END,}, }; -void __iomem *exynos5_list_both_cnt_feed[] = { +static void __iomem *exynos5_list_both_cnt_feed[] = { EXYNOS5_ARM_CORE0_OPTION, EXYNOS5_ARM_CORE1_OPTION, EXYNOS5_ARM_COMMON_OPTION, @@ -329,7 +329,7 @@ void __iomem *exynos5_list_both_cnt_feed[] = { EXYNOS5_TOP_PWR_SYSMEM_OPTION, }; -void __iomem *exynos5_list_diable_wfi_wfe[] = { +static void __iomem *exynos5_list_diable_wfi_wfe[] = { EXYNOS5_ARM_CORE1_OPTION, EXYNOS5_FSYS_ARM_OPTION, EXYNOS5_ISP_ARM_OPTION, From 2aa1ecf731fc4211a6b453167dff44c778789743 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 12 Jul 2012 16:57:19 +0900 Subject: [PATCH 5/5] ARM: SAMSUNG: Introduce Kconfig variable for Samsung custom clk API Make it easier to switch to the common clock API by making the existing clock API implementation depend on a Kconfig symbol which is enabled when the common clock API is disabled. This means that we can have some SoCs using the common clock API and some using the existing API rather than needing a flag day to convert the entire family of devices over. Signed-off-by: Mark Brown Acked-by: Heiko Stuebner Signed-off-by: Kukjin Kim --- arch/arm/plat-samsung/Kconfig | 4 ++++ arch/arm/plat-samsung/Makefile | 4 ++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index a2fae4ea0936..9b4cfd412b1b 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -78,6 +78,10 @@ config S5P_HRT # clock options +config SAMSUNG_CLOCK + bool + default y if !COMMON_CLK + config SAMSUNG_CLKSRC bool help diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 860b2db4db15..abf2f3b66988 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile @@ -15,8 +15,8 @@ obj-y += init.o cpu.o obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o obj-$(CONFIG_S5P_HRT) += s5p-time.o -obj-y += clock.o -obj-y += pwm-clock.o +obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o +obj-$(CONFIG_SAMSUNG_CLOCK) += pwm-clock.o obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o