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[ARM] add Marvell 78xx0 ARM SoC support

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The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring
(depending on the model) one or two Feroceon CPU cores with 512K of L2
cache and VFP coprocessors running at (depending on the model) between
800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe
interfaces that can each run either in x4 or quad x1 mode, three USB
2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two
TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI
interface, four UARTs, and depending on the model, two or four gigabit
ethernet interfaces.

This patch adds basic support for the platform, and allows booting
on the MV78x00 development board, with functional UARTs, SATA, PCIe,
GigE and USB ports.

Signed-off-by: Stanislav Samsonov <samsonov@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
This commit is contained in:
Stanislav Samsonov
2008-06-22 22:45:10 +02:00
committed by Lennert Buytenhek
parent a9311cfed2
commit 794d15b25d
24 changed files with 1856 additions and 2 deletions
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4
arch/arm/mm/Kconfig
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@@ -365,7 +365,7 @@ config CPU_XSC3
# Feroceon
config CPU_FEROCEON
bool
depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD
depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0
default y
select CPU_32v5
select CPU_ABRT_EV5T
@@ -716,7 +716,7 @@ config OUTER_CACHE
config CACHE_FEROCEON_L2
bool "Enable the Feroceon L2 cache controller"
depends on ARCH_KIRKWOOD
depends on ARCH_KIRKWOOD || ARCH_MV78XX0
default y
select OUTER_CACHE
help