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drm/nouveau: fix semaphore dmabuf obj

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Fixes some dmabuf object errors on nv50 chipset and below.

Cc: stable@vger.kernel.org [3.7+]
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Maarten Lankhorst
2013-07-23 15:49:39 +02:00
committed by Ben Skeggs
parent e0bacd2f7e
commit 7a7da592cb
2 changed files with 10 additions and 6 deletions
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2
drivers/gpu/drm/nouveau/nv17_fence.c
View File

@@ -76,7 +76,7 @@ nv17_fence_context_new(struct nouveau_channel *chan)
struct ttm_mem_reg *mem = &priv->bo->bo.mem; struct ttm_mem_reg *mem = &priv->bo->bo.mem;
struct nouveau_object *object; struct nouveau_object *object;
u32 start = mem->start * PAGE_SIZE; u32 start = mem->start * PAGE_SIZE;
u32 limit = mem->start + mem->size - 1; u32 limit = start + mem->size - 1;
int ret = 0; int ret = 0;
fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);

14
drivers/gpu/drm/nouveau/nv50_fence.c
View File

@@ -39,6 +39,8 @@ nv50_fence_context_new(struct nouveau_channel *chan)
struct nv10_fence_chan *fctx; struct nv10_fence_chan *fctx;
struct ttm_mem_reg *mem = &priv->bo->bo.mem; struct ttm_mem_reg *mem = &priv->bo->bo.mem;
struct nouveau_object *object; struct nouveau_object *object;
u32 start = mem->start * PAGE_SIZE;
u32 limit = start + mem->size - 1;
int ret, i; int ret, i;
fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
@@ -51,26 +53,28 @@ nv50_fence_context_new(struct nouveau_channel *chan)
fctx->base.sync = nv17_fence_sync; fctx->base.sync = nv17_fence_sync;
ret = nouveau_object_new(nv_object(chan->cli), chan->handle, ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
NvSema, 0x0002, NvSema, 0x003d,
&(struct nv_dma_class) { &(struct nv_dma_class) {
.flags = NV_DMA_TARGET_VRAM | .flags = NV_DMA_TARGET_VRAM |
NV_DMA_ACCESS_RDWR, NV_DMA_ACCESS_RDWR,
.start = mem->start * PAGE_SIZE, .start = start,
.limit = mem->size - 1, .limit = limit,
}, sizeof(struct nv_dma_class), }, sizeof(struct nv_dma_class),
&object); &object);
/* dma objects for display sync channel semaphore blocks */ /* dma objects for display sync channel semaphore blocks */
for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) { for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
u32 start = bo->bo.mem.start * PAGE_SIZE;
u32 limit = start + bo->bo.mem.size - 1;
ret = nouveau_object_new(nv_object(chan->cli), chan->handle, ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
NvEvoSema0 + i, 0x003d, NvEvoSema0 + i, 0x003d,
&(struct nv_dma_class) { &(struct nv_dma_class) {
.flags = NV_DMA_TARGET_VRAM | .flags = NV_DMA_TARGET_VRAM |
NV_DMA_ACCESS_RDWR, NV_DMA_ACCESS_RDWR,
.start = bo->bo.offset, .start = start,
.limit = bo->bo.offset + 0xfff, .limit = limit,
}, sizeof(struct nv_dma_class), }, sizeof(struct nv_dma_class),
&object); &object);
} }