[MTD] Refactor NAND hwcontrol to cmd_ctrl
The hwcontrol function enforced a step by step state machine for any kind of hardware chip access. Let the hardware driver know which control bits are set and inform it about a change of the control lines. Let the hardware driver write out the command and address bytes directly. This gives a peformance advantage for address bus controlled chips and simplifies the quirks in the hardware drivers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@@ -82,20 +82,27 @@ static const struct mtd_partition partition_info[] = {
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/*
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* hardware specific access to control-lines
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*/
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*
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* ctrl:
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* NAND_CNE: bit 0 -> bit 2
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* NAND_CLE: bit 1 -> bit 0
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* NAND_ALE: bit 2 -> bit 1
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*/
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static void spia_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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switch (cmd) {
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struct nand_chip *chip = mtd->priv;
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case NAND_CTL_SETCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x01; break;
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case NAND_CTL_CLRCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x01; break;
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if (ctrl & NAND_CTRL_CHANGE) {
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void __iomem *addr = spia_io_base + spia_pedr;
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unsigned char bits;
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case NAND_CTL_SETALE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x02; break;
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case NAND_CTL_CLRALE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x02; break;
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case NAND_CTL_SETNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x04; break;
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case NAND_CTL_CLRNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x04; break;
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bits = (ctrl & NAND_CNE) << 2;
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bits |= (ctrl & NAND_CLE | NAND_ALE) >> 1;
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writeb((readb(addr) & ~0x7) | bits, addr);
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, chip->IO_ADDR_W);
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}
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/*
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@@ -133,7 +140,7 @@ static int __init spia_init(void)
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this->IO_ADDR_R = (void __iomem *)spia_fio_base;
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this->IO_ADDR_W = (void __iomem *)spia_fio_base;
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/* Set address of hardware control function */
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this->hwcontrol = spia_hwcontrol;
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this->cmd_ctrl = spia_hwcontrol;
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/* 15 us command delay time */
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this->chip_delay = 15;
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