ssb: Fix pcicore cardbus mode
This fixes the pcicore driver to not die a horrible crash death when inserting a cardbus card. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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committed by
John W. Linville
parent
53521d8c90
commit
7cb4461520
@@ -282,6 +282,8 @@ struct ssb_bus {
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struct ssb_boardinfo boardinfo;
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/* Contents of the SPROM. */
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struct ssb_sprom sprom;
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/* If the board has a cardbus slot, this is set to true. */
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bool has_cardbus_slot;
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#ifdef CONFIG_SSB_EMBEDDED
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/* Lock for GPIO register access. */
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@@ -299,8 +301,13 @@ struct ssb_bus {
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/* The initialization-invariants. */
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struct ssb_init_invariants {
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/* Versioning information about the PCB. */
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struct ssb_boardinfo boardinfo;
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/* The SPROM information. That's either stored in an
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* EEPROM or NVRAM on the board. */
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struct ssb_sprom sprom;
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/* If the board has a cardbus slot, this is set to true. */
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bool has_cardbus_slot;
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};
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/* Type of function to fetch the invariants. */
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typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus,
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@@ -51,6 +51,11 @@
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#define SSB_PCICORE_SBTOPCI1_MASK 0xFC000000
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#define SSB_PCICORE_SBTOPCI2 0x0108 /* Backplane to PCI translation 2 (sbtopci2) */
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#define SSB_PCICORE_SBTOPCI2_MASK 0xC0000000
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#define SSB_PCICORE_PCICFG0 0x0400 /* PCI config space 0 (rev >= 8) */
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#define SSB_PCICORE_PCICFG1 0x0500 /* PCI config space 1 (rev >= 8) */
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#define SSB_PCICORE_PCICFG2 0x0600 /* PCI config space 2 (rev >= 8) */
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#define SSB_PCICORE_PCICFG3 0x0700 /* PCI config space 3 (rev >= 8) */
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#define SSB_PCICORE_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2)) /* SPROM shadow area (72 bytes) */
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/* SBtoPCIx */
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#define SSB_PCICORE_SBTOPCI_MEM 0x00000000
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