ARM: hw_breakpoint: disable preemption during debug exception handling
On ARM, debug exceptions occur in the form of data or prefetch aborts. One difference is that debug exceptions require access to per-cpu banked registers and data structures which are not saved in the low-level exception code. For kernels built with CONFIG_PREEMPT, there is an unlikely scenario that the debug handler ends up running on a different CPU from the one that originally signalled the event, resulting in random data being read from the wrong registers. This patch adds a debug_entry macro to the low-level exception handling code which checks whether the taken exception is a debug exception. If it is, the preempt count for the faulting process is incremented. After the debug handler has finished, the count is decremented. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@@ -24,6 +24,7 @@
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#define pr_fmt(fmt) "hw-breakpoint: " fmt
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#include <linux/errno.h>
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#include <linux/hardirq.h>
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#include <linux/perf_event.h>
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#include <linux/hw_breakpoint.h>
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#include <linux/smp.h>
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@@ -736,14 +737,17 @@ unlock:
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/*
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* Called from either the Data Abort Handler [watchpoint] or the
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* Prefetch Abort Handler [breakpoint].
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* Prefetch Abort Handler [breakpoint] with preemption disabled.
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*/
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static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
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struct pt_regs *regs)
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{
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int ret = 1; /* Unhandled fault. */
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int ret = 0;
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u32 dscr;
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/* We must be called with preemption disabled. */
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WARN_ON(preemptible());
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/* We only handle watchpoints and hardware breakpoints. */
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ARM_DBG_READ(c1, 0, dscr);
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@@ -758,11 +762,15 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
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watchpoint_handler(addr, regs);
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break;
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default:
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goto out;
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ret = 1; /* Unhandled fault. */
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}
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ret = 0;
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out:
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/*
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* Re-enable preemption after it was disabled in the
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* low-level exception handling code.
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*/
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preempt_enable();
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return ret;
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}
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