dsp56k: use request_firmware
Signed-off-by: Jaswinder Singh <jaswinder@infradead.org> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Jaswinder Singh
committed by
David Woodhouse
David Woodhouse
parent
d12b219a22
commit
7f127d5ed0
@ -20,6 +20,7 @@ fw-external-y := $(subst ",,$(CONFIG_EXTRA_FIRMWARE))
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# accurate. In the latter case it doesn't matter -- it'll use $(fw-shipped-all).
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# But be aware that the config file might not be included at all.
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fw-shipped-$(CONFIG_ATARI_DSP56K) += dsp56k/bootstrap.bin
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fw-shipped-$(CONFIG_ATM_AMBASSADOR) += atmsar11.fw
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fw-shipped-$(CONFIG_COMPUTONE) += intelliport2.bin
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fw-shipped-$(CONFIG_DVB_TTUSB_BUDGET) += ttusb-budget/dspbootcode.bin
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@ -309,3 +309,15 @@ Licence:
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Found in hex form in kernel source.
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--------------------------------------------------------------------------
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Driver: ATARI_DSP56K - Atari DSP56k support
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File: dsp56k/bootstrap.bin
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Source: dsp56k/bootstrap.asm
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Licence: GPLv2 or later
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DSP56001 assembler, possibly buildable with a56 from
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http://www.zdomain.com/a56.html
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--------------------------------------------------------------------------
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98
firmware/dsp56k/bootstrap.asm
Normal file
98
firmware/dsp56k/bootstrap.asm
Normal file
@ -0,0 +1,98 @@
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; Author: Frederik Noring <noring@nocrew.org>
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;
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; This file is subject to the terms and conditions of the GNU General Public
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; License. See the file COPYING in the main directory of this archive
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; for more details.
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; DSP56k loader
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; Host Interface
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M_BCR EQU $FFFE ; Port A Bus Control Register
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M_PBC EQU $FFE0 ; Port B Control Register
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M_PBDDR EQU $FFE2 ; Port B Data Direction Register
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M_PBD EQU $FFE4 ; Port B Data Register
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M_PCC EQU $FFE1 ; Port C Control Register
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M_PCDDR EQU $FFE3 ; Port C Data Direction Register
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M_PCD EQU $FFE5 ; Port C Data Register
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M_HCR EQU $FFE8 ; Host Control Register
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M_HSR EQU $FFE9 ; Host Status Register
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M_HRX EQU $FFEB ; Host Receive Data Register
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M_HTX EQU $FFEB ; Host Transmit Data Register
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; SSI, Synchronous Serial Interface
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M_RX EQU $FFEF ; Serial Receive Data Register
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M_TX EQU $FFEF ; Serial Transmit Data Register
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M_CRA EQU $FFEC ; SSI Control Register A
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M_CRB EQU $FFED ; SSI Control Register B
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M_SR EQU $FFEE ; SSI Status Register
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M_TSR EQU $FFEE ; SSI Time Slot Register
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; Exception Processing
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M_IPR EQU $FFFF ; Interrupt Priority Register
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org P:$0
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start jmp <$40
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org P:$40
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; ; Zero 16384 DSP X and Y words
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; clr A #0,r0
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; clr B #0,r4
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; do #64,<_block1
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; rep #256
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; move A,X:(r0)+ B,Y:(r4)+
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;_block1 ; Zero (32768-512) Program words
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; clr A #512,r0
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; do #126,<_block2
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; rep #256
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; move A,P:(r0)+
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;_block2
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; Copy DSP program control
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move #real,r0
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move #upload,r1
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do #upload_end-upload,<_copy
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move P:(r0)+,x0
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move x0,P:(r1)+
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_copy movep #>4,X:<<M_HCR
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movep #>$c00,X:<<M_IPR
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and #<$fe,mr
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jmp upload
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real
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org P:$7ea9
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upload
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movep #>1,X:<<M_PBC
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movep #>0,X:<<M_BCR
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next jclr #0,X:<<M_HSR,*
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movep X:<<M_HRX,A
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move #>3,x0
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cmp x0,A #>1,x0
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jeq <$0
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_get_address
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jclr #0,X:<<M_HSR,_get_address
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movep X:<<M_HRX,r0
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_get_length
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jclr #0,X:<<M_HSR,_get_length
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movep X:<<M_HRX,y0
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cmp x0,A #>2,x0
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jeq load_X
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cmp x0,A
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jeq load_Y
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load_P do y0,_load
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jclr #0,X:<<M_HSR,*
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movep X:<<M_HRX,P:(r0)+
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_load jmp next
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load_X do y0,_load
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jclr #0,X:<<M_HSR,*
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movep X:<<M_HRX,X:(r0)+
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_load jmp next
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load_Y do y0,_load
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jclr #0,X:<<M_HSR,*
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movep X:<<M_HRX,Y:(r0)+
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_load jmp next
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upload_end
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end
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26
firmware/dsp56k/bootstrap.bin.ihex
Normal file
26
firmware/dsp56k/bootstrap.bin.ihex
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@ -0,0 +1,26 @@
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:100000000C004000000000000000000000000000A4
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:1000100000000000000000000000000000000000E0
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:1000200000000000000000000000000000000000D0
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:1000300000000000000000000000000000000000C0
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:1000400000000000000000000000000000000000B0
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:1000500000000000000000000000000000000000A0
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:100060000000000000000000000000000000000090
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:100070000000000000000000000000000000000080
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:100080000000000000000000000000000000000070
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:100090000000000000000000000000000000000060
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:1000A0000000000000000000000000000000000050
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:1000B0000000000000000000000000000000000040
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:1000C00060F40000004F61F400007EA9062E80005D
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:1000D000004707D88407598408F4A800000408F4EE
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:1000E000BF000C0000FEB80AF080007EA908F4A052
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:1000F00000000108F4BE0000000AA980007EAD08DF
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:100100004E2B44F40000000344F4450000010EA00F
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:10011000000AA980007EB508502B0AA980007EB88D
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:1001200008462B44F4450000020AF0AA007EC920CC
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:1001300000450AF0AA007ED006C600007EC60AA9C5
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:1001400080007EC408586B0AF080007EAD06C600B1
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:10015000007ECD0AA980007ECB0858AB0AF0800053
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:100160007EAD06C600007ED40AA980007ED2085863
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:07017000EB0AF080007EADF8
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:00000001FF
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/* DSP56001 bootstrap code */
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