[PATCH] MCA/INIT: use per cpu stacks
The bulk of the change. Use per cpu MCA/INIT stacks. Change the SAL to OS state (sos) to be per process. Do all the assembler work on the MCA/INIT stacks, leaving the original stack alone. Pass per cpu state data to the C handlers for MCA and INIT, which also means changing the mca_drv interfaces slightly. Lots of verification on whether the original stack is usable before converting it to a sleeping process. Signed-off-by: Keith Owens <kaos@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Keith Owens
Tony Luck
@@ -8,6 +8,8 @@
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* Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
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* Copyright (C) 2002 Intel Corp.
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* Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
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* Copyright (C) 2005 Silicon Graphics, Inc
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* Copyright (C) 2005 Keith Owens <kaos@sgi.com>
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*/
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#ifndef _ASM_IA64_MCA_ASM_H
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#define _ASM_IA64_MCA_ASM_H
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@@ -207,106 +209,33 @@
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;;
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/*
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* The following offsets capture the order in which the
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* RSE related registers from the old context are
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* saved onto the new stack frame.
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* The MCA and INIT stacks in struct ia64_mca_cpu look like normal kernel
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* stacks, except that the SAL/OS state and a switch_stack are stored near the
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* top of the MCA/INIT stack. To support concurrent entry to MCA or INIT, as
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* well as MCA over INIT, each event needs its own SAL/OS state. All entries
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* are 16 byte aligned.
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*
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* +-----------------------+
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* |NDIRTY [BSP - BSPSTORE]|
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* +-----------------------+
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* | RNAT |
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* +-----------------------+
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* | BSPSTORE |
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* +-----------------------+
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* | IFS |
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* +-----------------------+
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* | PFS |
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* +-----------------------+
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* | RSC |
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* +-----------------------+ <-------- Bottom of new stack frame
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* +---------------------------+
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* | pt_regs |
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* +---------------------------+
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* | switch_stack |
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* +---------------------------+
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* | SAL/OS state |
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* +---------------------------+
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* | 16 byte scratch area |
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* +---------------------------+ <-------- SP at start of C MCA handler
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* | ..... |
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* +---------------------------+
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* | RBS for MCA/INIT handler |
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* +---------------------------+
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* | struct task for MCA/INIT |
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* +---------------------------+ <-------- Bottom of MCA/INIT stack
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*/
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#define rse_rsc_offset 0
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#define rse_pfs_offset (rse_rsc_offset+0x08)
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#define rse_ifs_offset (rse_pfs_offset+0x08)
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#define rse_bspstore_offset (rse_ifs_offset+0x08)
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#define rse_rnat_offset (rse_bspstore_offset+0x08)
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#define rse_ndirty_offset (rse_rnat_offset+0x08)
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/*
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* rse_switch_context
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*
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* 1. Save old RSC onto the new stack frame
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* 2. Save PFS onto new stack frame
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* 3. Cover the old frame and start a new frame.
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* 4. Save IFS onto new stack frame
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* 5. Save the old BSPSTORE on the new stack frame
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* 6. Save the old RNAT on the new stack frame
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* 7. Write BSPSTORE with the new backing store pointer
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* 8. Read and save the new BSP to calculate the #dirty registers
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* NOTE: Look at pages 11-10, 11-11 in PRM Vol 2
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*/
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#define rse_switch_context(temp,p_stackframe,p_bspstore) \
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;; \
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mov temp=ar.rsc;; \
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st8 [p_stackframe]=temp,8;; \
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mov temp=ar.pfs;; \
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st8 [p_stackframe]=temp,8; \
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cover ;; \
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mov temp=cr.ifs;; \
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st8 [p_stackframe]=temp,8;; \
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mov temp=ar.bspstore;; \
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st8 [p_stackframe]=temp,8;; \
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mov temp=ar.rnat;; \
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st8 [p_stackframe]=temp,8; \
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mov ar.bspstore=p_bspstore;; \
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mov temp=ar.bsp;; \
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sub temp=temp,p_bspstore;; \
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st8 [p_stackframe]=temp,8;;
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/*
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* rse_return_context
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* 1. Allocate a zero-sized frame
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* 2. Store the number of dirty registers RSC.loadrs field
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* 3. Issue a loadrs to insure that any registers from the interrupted
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* context which were saved on the new stack frame have been loaded
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* back into the stacked registers
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* 4. Restore BSPSTORE
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* 5. Restore RNAT
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* 6. Restore PFS
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* 7. Restore IFS
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* 8. Restore RSC
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* 9. Issue an RFI
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*/
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#define rse_return_context(psr_mask_reg,temp,p_stackframe) \
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;; \
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alloc temp=ar.pfs,0,0,0,0; \
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add p_stackframe=rse_ndirty_offset,p_stackframe;; \
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ld8 temp=[p_stackframe];; \
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shl temp=temp,16;; \
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mov ar.rsc=temp;; \
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loadrs;; \
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add p_stackframe=-rse_ndirty_offset+rse_bspstore_offset,p_stackframe;;\
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ld8 temp=[p_stackframe];; \
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mov ar.bspstore=temp;; \
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add p_stackframe=-rse_bspstore_offset+rse_rnat_offset,p_stackframe;;\
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ld8 temp=[p_stackframe];; \
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mov ar.rnat=temp;; \
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add p_stackframe=-rse_rnat_offset+rse_pfs_offset,p_stackframe;; \
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ld8 temp=[p_stackframe];; \
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mov ar.pfs=temp;; \
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add p_stackframe=-rse_pfs_offset+rse_ifs_offset,p_stackframe;; \
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ld8 temp=[p_stackframe];; \
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mov cr.ifs=temp;; \
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add p_stackframe=-rse_ifs_offset+rse_rsc_offset,p_stackframe;; \
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ld8 temp=[p_stackframe];; \
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mov ar.rsc=temp ; \
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mov temp=psr;; \
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or temp=temp,psr_mask_reg;; \
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mov cr.ipsr=temp;; \
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mov temp=ip;; \
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add temp=0x30,temp;; \
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mov cr.iip=temp;; \
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srlz.i;; \
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rfi;;
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#define ALIGN16(x) ((x)&~15)
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#define MCA_PT_REGS_OFFSET ALIGN16(KERNEL_STACK_SIZE-IA64_PT_REGS_SIZE)
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#define MCA_SWITCH_STACK_OFFSET ALIGN16(MCA_PT_REGS_OFFSET-IA64_SWITCH_STACK_SIZE)
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#define MCA_SOS_OFFSET ALIGN16(MCA_SWITCH_STACK_OFFSET-IA64_SAL_OS_STATE_SIZE)
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#define MCA_SP_OFFSET ALIGN16(MCA_SOS_OFFSET-16)
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#endif /* _ASM_IA64_MCA_ASM_H */
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