Merge branch 'tip/perf/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-2.6-trace into perf/core
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@ -593,8 +593,12 @@ static int x86_setup_perfctr(struct perf_event *event)
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return -EOPNOTSUPP;
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}
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/*
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* Do not allow config1 (extended registers) to propagate,
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* there's no sane user-space generalization yet:
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*/
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if (attr->type == PERF_TYPE_RAW)
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return x86_pmu_extra_regs(event->attr.config, event);
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return 0;
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if (attr->type == PERF_TYPE_HW_CACHE)
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return set_ext_hw_attr(hwc, event);
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@ -616,8 +620,8 @@ static int x86_setup_perfctr(struct perf_event *event)
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/*
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* Branch tracing:
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*/
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if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
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(hwc->sample_period == 1)) {
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if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
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!attr->freq && hwc->sample_period == 1) {
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/* BTS is not supported by this architecture. */
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if (!x86_pmu.bts_active)
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return -EOPNOTSUPP;
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@ -1291,6 +1295,16 @@ static int x86_pmu_handle_irq(struct pt_regs *regs)
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cpuc = &__get_cpu_var(cpu_hw_events);
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/*
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* Some chipsets need to unmask the LVTPC in a particular spot
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* inside the nmi handler. As a result, the unmasking was pushed
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* into all the nmi handlers.
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*
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* This generic handler doesn't seem to have any issues where the
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* unmasking occurs so it was left at the top.
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*/
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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for (idx = 0; idx < x86_pmu.num_counters; idx++) {
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if (!test_bit(idx, cpuc->active_mask)) {
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/*
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@ -1377,8 +1391,6 @@ perf_event_nmi_handler(struct notifier_block *self,
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return NOTIFY_DONE;
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}
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apic_write(APIC_LVTPC, APIC_DM_NMI);
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handled = x86_pmu.handle_irq(args->regs);
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if (!handled)
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return NOTIFY_DONE;
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