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x86/amd-iommu: Export cache-coherency capability

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This patch exports the capability of the AMD IOMMU to force
cache coherency of DMA transactions through the IOMMU-API.
This is required to disable some nasty hacks in KVM when
this capability is not available.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
This commit is contained in:
Joerg Roedel
2010-07-27 17:14:24 +02:00
parent 6c54aabd5e
commit 80a506b8fd
1 changed files with 5 additions and 0 deletions
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arch/x86/kernel/amd_iommu.c
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@@ -2572,6 +2572,11 @@ static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
static int amd_iommu_domain_has_cap(struct iommu_domain *domain, static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
unsigned long cap) unsigned long cap)
{ {
switch (cap) {
case IOMMU_CAP_CACHE_COHERENCY:
return 1;
}
return 0; return 0;
} }