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sfc: Treat all MAC registers as 128-bit

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Although all the defined fields in these registers are within 32 bits,
they are architecturally defined as 128-bit like most other Falcon
registers.  In particular, we must use efx_reado() to ensure proper
locking when reading MD_STAT_REG.

Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ben Hutchings
2009-11-25 16:08:41 +00:00
committed by David S. Miller
parent 46e1ac0f42
commit 80cb9a0f7f
2 changed files with 14 additions and 14 deletions
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14
drivers/net/sfc/falcon.c
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@@ -2042,18 +2042,18 @@ int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
/* Wait for GMII access to complete */
static int falcon_gmii_wait(struct efx_nic *efx)
{
efx_dword_t md_stat;
efx_oword_t md_stat;
int count;
/* wait upto 50ms - taken max from datasheet */
for (count = 0; count < 5000; count++) {
efx_readd(efx, &md_stat, FR_AB_MD_STAT);
if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
efx_reado(efx, &md_stat, FR_AB_MD_STAT);
if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
EFX_ERR(efx, "error from GMII access "
EFX_DWORD_FMT"\n",
EFX_DWORD_VAL(md_stat));
EFX_OWORD_FMT"\n",
EFX_OWORD_VAL(md_stat));
return -EIO;
}
return 0;