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x86: add PCI extended config space access for AMD Barcelona

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This patch implements PCI extended configuration space access for
AMD's Barcelona CPUs. It extends the method using CF8/CFC IO
addresses. An x86 capability bit has been introduced that is set for
CPUs supporting PCI extended config space accesses.

Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Robert Richter
2007-09-03 10:17:39 +02:00
committed by Ingo Molnar
parent 1c47cd638e
commit 831d991821
7 changed files with 65 additions and 6 deletions
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4
arch/x86/kernel/cpu/amd.c
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@@ -6,6 +6,7 @@
#include <asm/apic.h>
#include <mach_apic.h>
#include "../setup.h"
#include "cpu.h"
/*
@@ -308,6 +309,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
if (cpu_has_xmm2)
set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
if (c->x86 == 0x10)
amd_enable_pci_ext_cfg(c);
}
static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)