Blackfin arch: unify differences between our diff head.S files -- no functional changes
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
@@ -51,9 +51,10 @@ ENTRY(__start)
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ENTRY(__stext)
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ENTRY(__stext)
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/* R0: argument of command line string, passed from uboot, save it */
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/* R0: argument of command line string, passed from uboot, save it */
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R7 = R0;
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R7 = R0;
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/* Set the SYSCFG register */
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/* Set the SYSCFG register:
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* Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
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*/
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R0 = 0x36;
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R0 = 0x36;
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/*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
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SYSCFG = R0;
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SYSCFG = R0;
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R0 = 0;
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R0 = 0;
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@@ -439,8 +440,8 @@ ENTRY(_start_dma_code)
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p0.h = hi(SIC_IWR);
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p0.h = hi(SIC_IWR);
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p0.l = lo(SIC_IWR);
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p0.l = lo(SIC_IWR);
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r0.l = lo(IWR_ENABLE_ALL)
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r0.l = lo(IWR_ENABLE_ALL);
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r0.h = hi(IWR_ENABLE_ALL)
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r0.h = hi(IWR_ENABLE_ALL);
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[p0] = r0;
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[p0] = r0;
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SSYNC;
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SSYNC;
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@@ -48,9 +48,11 @@ ENTRY(__start)
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ENTRY(__stext)
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ENTRY(__stext)
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/* R0: argument of command line string, passed from uboot, save it */
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/* R0: argument of command line string, passed from uboot, save it */
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R7 = R0;
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R7 = R0;
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/* Set the SYSCFG register */
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/* Set the SYSCFG register:
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* Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
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*/
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R0 = 0x36;
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R0 = 0x36;
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SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
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SYSCFG = R0;
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R0 = 0;
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R0 = 0;
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/* Clear Out All the data and pointer Registers */
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/* Clear Out All the data and pointer Registers */
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@@ -191,7 +193,7 @@ ENTRY(__stext)
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p0.h = hi(UART_DLL);
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p0.h = hi(UART_DLL);
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p0.l = lo(UART_DLL);
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p0.l = lo(UART_DLL);
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r0 = 0x00(Z);
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r0 = 0x0(Z);
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w[p0] = r0.L;
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w[p0] = r0.L;
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ssync;
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ssync;
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@@ -218,6 +220,7 @@ ENTRY(__stext)
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#if CONFIG_BFIN_KERNEL_CLOCK
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#if CONFIG_BFIN_KERNEL_CLOCK
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call _start_dma_code;
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call _start_dma_code;
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#endif
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#endif
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/* Code for initializing Async memory banks */
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/* Code for initializing Async memory banks */
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p2.h = hi(EBIU_AMBCTL1);
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p2.h = hi(EBIU_AMBCTL1);
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@@ -328,7 +331,6 @@ ENTRY(_real_start)
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r1 = p3;
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r1 = p3;
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[p1] = r1;
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[p1] = r1;
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/*
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/*
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* load the current thread pointer and stack
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* load the current thread pointer and stack
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*/
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*/
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@@ -48,9 +48,11 @@ ENTRY(__start)
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ENTRY(__stext)
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ENTRY(__stext)
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/* R0: argument of command line string, passed from uboot, save it */
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/* R0: argument of command line string, passed from uboot, save it */
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R7 = R0;
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R7 = R0;
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/* Set the SYSCFG register */
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/* Set the SYSCFG register:
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* Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
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*/
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R0 = 0x36;
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R0 = 0x36;
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SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
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SYSCFG = R0;
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R0 = 0;
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R0 = 0;
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/* Clear Out All the data and pointer Registers */
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/* Clear Out All the data and pointer Registers */
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