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Blackfin arch: unify differences between our diff head.S files -- no functional changes

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Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
Mike Frysinger
2007-06-11 15:31:30 +08:00
committed by Bryan Wu
parent 16983de0ce
commit 83a5c3e321
3 changed files with 32 additions and 27 deletions
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9
arch/blackfin/mach-bf533/head.S
View File

@@ -51,9 +51,10 @@ ENTRY(__start)
ENTRY(__stext)
/* R0: argument of command line string, passed from uboot, save it */
R7 = R0;
/* Set the SYSCFG register */
/* Set the SYSCFG register:
* Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
*/
R0 = 0x36;
/*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
SYSCFG = R0;
R0 = 0;
@@ -439,8 +440,8 @@ ENTRY(_start_dma_code)
p0.h = hi(SIC_IWR);
p0.l = lo(SIC_IWR);
r0.l = lo(IWR_ENABLE_ALL)
r0.h = hi(IWR_ENABLE_ALL)
r0.l = lo(IWR_ENABLE_ALL);
r0.h = hi(IWR_ENABLE_ALL);
[p0] = r0;
SSYNC;

10
arch/blackfin/mach-bf537/head.S
View File

@@ -48,9 +48,11 @@ ENTRY(__start)
ENTRY(__stext)
/* R0: argument of command line string, passed from uboot, save it */
R7 = R0;
/* Set the SYSCFG register */
/* Set the SYSCFG register:
* Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
*/
R0 = 0x36;
SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
SYSCFG = R0;
R0 = 0;
/* Clear Out All the data and pointer Registers */
@@ -191,7 +193,7 @@ ENTRY(__stext)
p0.h = hi(UART_DLL);
p0.l = lo(UART_DLL);
r0 = 0x00(Z);
r0 = 0x0(Z);
w[p0] = r0.L;
ssync;
@@ -218,6 +220,7 @@ ENTRY(__stext)
#if CONFIG_BFIN_KERNEL_CLOCK
call _start_dma_code;
#endif
/* Code for initializing Async memory banks */
p2.h = hi(EBIU_AMBCTL1);
@@ -328,7 +331,6 @@ ENTRY(_real_start)
r1 = p3;
[p1] = r1;
/*
* load the current thread pointer and stack
*/

6
arch/blackfin/mach-bf561/head.S
View File

@@ -48,9 +48,11 @@ ENTRY(__start)
ENTRY(__stext)
/* R0: argument of command line string, passed from uboot, save it */
R7 = R0;
/* Set the SYSCFG register */
/* Set the SYSCFG register:
* Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
*/
R0 = 0x36;
SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
SYSCFG = R0;
R0 = 0;
/* Clear Out All the data and pointer Registers */