MIPS: JZ4740: Add base support for Ingenic JZ4740 System-on-a-Chip
Adds a new cpu type for the JZ4740 to the Linux MIPS architecture code. It also adds the iomem addresses for the different components found on a JZ4740 SoC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1464/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Ralf Baechle
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@ -34,7 +34,7 @@
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#define PRID_COMP_LSI 0x080000
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#define PRID_COMP_LEXRA 0x0b0000
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#define PRID_COMP_CAVIUM 0x0d0000
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#define PRID_COMP_INGENIC 0xd00000
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/*
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* Assigned values for the product ID register. In order to detect a
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@ -132,6 +132,12 @@
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#define PRID_IMP_CAVIUM_CN50XX 0x0600
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#define PRID_IMP_CAVIUM_CN52XX 0x0700
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/*
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* These are the PRID's for when 23:16 == PRID_COMP_INGENIC
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*/
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#define PRID_IMP_JZRISC 0x0200
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/*
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* Definitions for 7:0 on legacy processors
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*/
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@ -219,6 +225,7 @@ enum cpu_type_enum {
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CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
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CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
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CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358,
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CPU_JZRISC,
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/*
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* MIPS64 class processors
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