Merge branch 'sh/sdio' into sh-latest
This commit is contained in:
Paul Mundt
217
include/linux/mmc/dw_mmc.h
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217
include/linux/mmc/dw_mmc.h
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/*
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* Synopsys DesignWare Multimedia Card Interface driver
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* (Based on NXP driver for lpc 31xx)
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*
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* Copyright (C) 2009 NXP Semiconductors
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* Copyright (C) 2009, 2010 Imagination Technologies Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _LINUX_MMC_DW_MMC_H_
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#define _LINUX_MMC_DW_MMC_H_
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#define MAX_MCI_SLOTS 2
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enum dw_mci_state {
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STATE_IDLE = 0,
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STATE_SENDING_CMD,
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STATE_SENDING_DATA,
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STATE_DATA_BUSY,
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STATE_SENDING_STOP,
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STATE_DATA_ERROR,
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};
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enum {
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EVENT_CMD_COMPLETE = 0,
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EVENT_XFER_COMPLETE,
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EVENT_DATA_COMPLETE,
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EVENT_DATA_ERROR,
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EVENT_XFER_ERROR
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};
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struct mmc_data;
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/**
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* struct dw_mci - MMC controller state shared between all slots
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* @lock: Spinlock protecting the queue and associated data.
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* @regs: Pointer to MMIO registers.
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* @sg: Scatterlist entry currently being processed by PIO code, if any.
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* @pio_offset: Offset into the current scatterlist entry.
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* @cur_slot: The slot which is currently using the controller.
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* @mrq: The request currently being processed on @cur_slot,
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* or NULL if the controller is idle.
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* @cmd: The command currently being sent to the card, or NULL.
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* @data: The data currently being transferred, or NULL if no data
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* transfer is in progress.
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* @use_dma: Whether DMA channel is initialized or not.
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* @sg_dma: Bus address of DMA buffer.
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* @sg_cpu: Virtual address of DMA buffer.
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* @dma_ops: Pointer to platform-specific DMA callbacks.
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* @cmd_status: Snapshot of SR taken upon completion of the current
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* command. Only valid when EVENT_CMD_COMPLETE is pending.
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* @data_status: Snapshot of SR taken upon completion of the current
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* data transfer. Only valid when EVENT_DATA_COMPLETE or
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* EVENT_DATA_ERROR is pending.
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* @stop_cmdr: Value to be loaded into CMDR when the stop command is
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* to be sent.
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* @dir_status: Direction of current transfer.
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* @tasklet: Tasklet running the request state machine.
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* @card_tasklet: Tasklet handling card detect.
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* @pending_events: Bitmask of events flagged by the interrupt handler
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* to be processed by the tasklet.
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* @completed_events: Bitmask of events which the state machine has
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* processed.
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* @state: Tasklet state.
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* @queue: List of slots waiting for access to the controller.
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* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
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* rate and timeout calculations.
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* @current_speed: Configured rate of the controller.
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* @num_slots: Number of slots available.
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* @pdev: Platform device associated with the MMC controller.
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* @pdata: Platform data associated with the MMC controller.
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* @slot: Slots sharing this MMC controller.
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* @data_shift: log2 of FIFO item size.
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* @push_data: Pointer to FIFO push function.
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* @pull_data: Pointer to FIFO pull function.
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* @quirks: Set of quirks that apply to specific versions of the IP.
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*
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* Locking
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* =======
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*
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* @lock is a softirq-safe spinlock protecting @queue as well as
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* @cur_slot, @mrq and @state. These must always be updated
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* at the same time while holding @lock.
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*
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* The @mrq field of struct dw_mci_slot is also protected by @lock,
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* and must always be written at the same time as the slot is added to
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* @queue.
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*
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* @pending_events and @completed_events are accessed using atomic bit
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* operations, so they don't need any locking.
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*
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* None of the fields touched by the interrupt handler need any
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* locking. However, ordering is important: Before EVENT_DATA_ERROR or
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* EVENT_DATA_COMPLETE is set in @pending_events, all data-related
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* interrupts must be disabled and @data_status updated with a
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* snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
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* CMDRDY interupt must be disabled and @cmd_status updated with a
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* snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
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* bytes_xfered field of @data must be written. This is ensured by
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* using barriers.
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*/
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struct dw_mci {
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spinlock_t lock;
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void __iomem *regs;
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struct scatterlist *sg;
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unsigned int pio_offset;
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struct dw_mci_slot *cur_slot;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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/* DMA interface members*/
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int use_dma;
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dma_addr_t sg_dma;
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void *sg_cpu;
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struct dw_mci_dma_ops *dma_ops;
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#ifdef CONFIG_MMC_DW_IDMAC
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unsigned int ring_size;
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#else
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struct dw_mci_dma_data *dma_data;
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#endif
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u32 cmd_status;
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u32 data_status;
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u32 stop_cmdr;
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u32 dir_status;
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struct tasklet_struct tasklet;
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struct tasklet_struct card_tasklet;
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unsigned long pending_events;
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unsigned long completed_events;
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enum dw_mci_state state;
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struct list_head queue;
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u32 bus_hz;
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u32 current_speed;
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u32 num_slots;
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struct platform_device *pdev;
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struct dw_mci_board *pdata;
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struct dw_mci_slot *slot[MAX_MCI_SLOTS];
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/* FIFO push and pull */
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int data_shift;
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void (*push_data)(struct dw_mci *host, void *buf, int cnt);
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void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
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/* Workaround flags */
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u32 quirks;
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};
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/* DMA ops for Internal/External DMAC interface */
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struct dw_mci_dma_ops {
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/* DMA Ops */
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int (*init)(struct dw_mci *host);
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void (*start)(struct dw_mci *host, unsigned int sg_len);
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void (*complete)(struct dw_mci *host);
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void (*stop)(struct dw_mci *host);
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void (*cleanup)(struct dw_mci *host);
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void (*exit)(struct dw_mci *host);
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};
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/* IP Quirks/flags. */
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/* No special quirks or flags to cater for */
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#define DW_MCI_QUIRK_NONE 0
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/* DTO fix for command transmission with IDMAC configured */
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#define DW_MCI_QUIRK_IDMAC_DTO 1
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/* delay needed between retries on some 2.11a implementations */
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#define DW_MCI_QUIRK_RETRY_DELAY 2
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/* High Speed Capable - Supports HS cards (upto 50MHz) */
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#define DW_MCI_QUIRK_HIGHSPEED 4
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struct dma_pdata;
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struct block_settings {
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unsigned short max_segs; /* see blk_queue_max_segments */
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unsigned int max_blk_size; /* maximum size of one mmc block */
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unsigned int max_blk_count; /* maximum number of blocks in one req*/
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unsigned int max_req_size; /* maximum number of bytes in one req*/
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unsigned int max_seg_size; /* see blk_queue_max_segment_size */
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};
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/* Board platform data */
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struct dw_mci_board {
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u32 num_slots;
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u32 quirks; /* Workaround / Quirk flags */
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unsigned int bus_hz; /* Bus speed */
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/* delay in mS before detecting cards after interrupt */
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u32 detect_delay_ms;
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int (*init)(u32 slot_id, irq_handler_t , void *);
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int (*get_ro)(u32 slot_id);
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int (*get_cd)(u32 slot_id);
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int (*get_ocr)(u32 slot_id);
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int (*get_bus_wd)(u32 slot_id);
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/*
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* Enable power to selected slot and set voltage to desired level.
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* Voltage levels are specified using MMC_VDD_xxx defines defined
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* in linux/mmc/host.h file.
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*/
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void (*setpower)(u32 slot_id, u32 volt);
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void (*exit)(u32 slot_id);
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void (*select_slot)(u32 slot_id);
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struct dw_mci_dma_ops *dma_ops;
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struct dma_pdata *data;
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struct block_settings *blk_settings;
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};
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#endif /* _LINUX_MMC_DW_MMC_H_ */
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@@ -131,6 +131,9 @@ struct mmc_host {
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unsigned int f_max;
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unsigned int f_init;
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u32 ocr_avail;
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u32 ocr_avail_sdio; /* SDIO-specific OCR */
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u32 ocr_avail_sd; /* SD-specific OCR */
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u32 ocr_avail_mmc; /* MMC-specific OCR */
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struct notifier_block pm_notify;
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#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
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@@ -169,9 +172,20 @@ struct mmc_host {
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#define MMC_CAP_1_2V_DDR (1 << 12) /* can support */
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/* DDR mode at 1.2V */
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#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */
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#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */
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mmc_pm_flag_t pm_caps; /* supported pm features */
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#ifdef CONFIG_MMC_CLKGATE
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int clk_requests; /* internal reference counter */
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unsigned int clk_delay; /* number of MCI clk hold cycles */
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bool clk_gated; /* clock gated */
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struct work_struct clk_gate_work; /* delayed clock gate */
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unsigned int clk_old; /* old clock value cache */
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spinlock_t clk_lock; /* lock for clk fields */
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struct mutex clk_gate_mutex; /* mutex for clock gating */
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#endif
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/* host specific block data */
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unsigned int max_seg_size; /* see blk_queue_max_segment_size */
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unsigned short max_segs; /* see blk_queue_max_segments */
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@@ -307,5 +321,10 @@ static inline int mmc_card_is_removable(struct mmc_host *host)
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return !(host->caps & MMC_CAP_NONREMOVABLE) && mmc_assume_removable;
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}
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static inline int mmc_card_is_powered_resumed(struct mmc_host *host)
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{
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return host->pm_flags & MMC_PM_KEEP_POWER;
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}
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#endif
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@@ -40,7 +40,9 @@
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#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
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#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
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#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
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#define MMC_BUS_TEST_R 14 /* adtc R1 */
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#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
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#define MMC_BUS_TEST_W 19 /* adtc R1 */
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#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
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#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
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@@ -83,6 +83,8 @@ struct sdhci_host {
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#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
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/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
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#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
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/* Controller treats ADMA descriptors with length 0000h incorrectly */
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#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
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int irq; /* Device IRQ */
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void __iomem *ioaddr; /* Mapped address */
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@@ -139,6 +141,10 @@ struct sdhci_host {
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unsigned int caps; /* Alternative capabilities */
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unsigned int ocr_avail_sdio; /* OCR bit masks */
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unsigned int ocr_avail_sd;
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unsigned int ocr_avail_mmc;
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unsigned long private[0] ____cacheline_aligned;
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};
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#endif /* __SDHCI_H */
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