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ath5k: Fix bad udelay calls on AR5210 code

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* Fix bad udelay calls (using > 2000us) in AR5210 code and clean up
 some bits on nic_reset (AR5210 support is still in bad shape)

 Changes-licensed-under: ISC
 Signed-off-by: Nick Kossifidis <mickflemm@gmail.com>

Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Nick Kossifidis
2008-09-17 03:33:19 +03:00
committed by John W. Linville
parent 92ffe055c3
commit 84e463fa07
3 changed files with 14 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/wireless/ath5k/phy.c
View File

@@ -2124,7 +2124,7 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210); beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210); ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
udelay(2300); mdelay(2);
/* /*
* Set the channel (with AGC turned off) * Set the channel (with AGC turned off)

2
drivers/net/wireless/ath5k/reg.h
View File

@@ -820,8 +820,6 @@
#define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */ #define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */
#define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */ #define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */
#define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */ #define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */
#define AR5K_RESET_CTL_CHIP (AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA | \
AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY)
/* /*
* Sleep control register * Sleep control register

20
drivers/net/wireless/ath5k/reset.c
View File

@@ -173,8 +173,10 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
udelay(15); udelay(15);
if (ah->ah_version == AR5K_AR5210) { if (ah->ah_version == AR5K_AR5210) {
val &= AR5K_RESET_CTL_CHIP; val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
mask &= AR5K_RESET_CTL_CHIP; | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
| AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
} else { } else {
val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND; mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
@@ -361,16 +363,20 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI; bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
/* Reset chipset */ /* Reset chipset */
ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU | if (ah->ah_version == AR5K_AR5210) {
AR5K_RESET_CTL_BASEBAND | bus_flags); ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
mdelay(2);
} else {
ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
AR5K_RESET_CTL_BASEBAND | bus_flags);
}
if (ret) { if (ret) {
ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n"); ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
return -EIO; return -EIO;
} }
if (ah->ah_version == AR5K_AR5210)
udelay(2300);
/* ...wakeup again!*/ /* ...wakeup again!*/
ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0); ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
if (ret) { if (ret) {