ASoC: Add source argument to PLL configuration
More and more devices feature PLLs and FLLs with the ability to select between multiple input clocks. In order to better support these devices a new argument, source, has been added to the set_pll() configuration API. Using set_clkdiv() is often difficult due to the need to stop the PLL/FLL before any reconfiguration can be done. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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@ -2197,16 +2197,18 @@ EXPORT_SYMBOL_GPL(snd_soc_dai_set_clkdiv);
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* snd_soc_dai_set_pll - configure DAI PLL.
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* @dai: DAI
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* @pll_id: DAI specific PLL ID
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* @source: DAI specific source for the PLL
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* @freq_in: PLL input clock frequency in Hz
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* @freq_out: requested PLL output clock frequency in Hz
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*
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* Configures and enables PLL to generate output clock based on input clock.
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*/
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int snd_soc_dai_set_pll(struct snd_soc_dai *dai,
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int pll_id, unsigned int freq_in, unsigned int freq_out)
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int snd_soc_dai_set_pll(struct snd_soc_dai *dai, int pll_id, int source,
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unsigned int freq_in, unsigned int freq_out)
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{
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if (dai->ops && dai->ops->set_pll)
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return dai->ops->set_pll(dai, pll_id, freq_in, freq_out);
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return dai->ops->set_pll(dai, pll_id, source,
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freq_in, freq_out);
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else
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return -EINVAL;
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}
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