igb: move the tx and rx ring specific config into seperate functions
This change makes the tx and rx config a bit cleaner by breaking out the ring specific configuration from the generic rx and tx configuration. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
committed by
David S. Miller
parent
7d95b7170e
commit
85b430b477
@@ -87,9 +87,13 @@ struct vf_data_storage {
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* descriptors until either it has this many to write back, or the
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* descriptors until either it has this many to write back, or the
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* ITR timer expires.
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* ITR timer expires.
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*/
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*/
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#define IGB_RX_PTHRESH 16
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#define IGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8)
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#define IGB_RX_HTHRESH 8
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#define IGB_RX_HTHRESH 8
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#define IGB_RX_WTHRESH 1
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#define IGB_RX_WTHRESH 1
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#define IGB_TX_PTHRESH 8
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#define IGB_TX_HTHRESH 1
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#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
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adapter->msix_entries) ? 0 : 16)
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/* this is the size past which hardware will drop packets when setting LPE=0 */
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/* this is the size past which hardware will drop packets when setting LPE=0 */
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#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
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#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
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@@ -90,6 +90,7 @@ static int igb_open(struct net_device *);
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static int igb_close(struct net_device *);
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static int igb_close(struct net_device *);
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static void igb_configure_tx(struct igb_adapter *);
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static void igb_configure_tx(struct igb_adapter *);
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static void igb_configure_rx(struct igb_adapter *);
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static void igb_configure_rx(struct igb_adapter *);
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static void igb_setup_tctl(struct igb_adapter *);
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static void igb_setup_rctl(struct igb_adapter *);
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static void igb_setup_rctl(struct igb_adapter *);
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static void igb_clean_all_tx_rings(struct igb_adapter *);
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static void igb_clean_all_tx_rings(struct igb_adapter *);
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static void igb_clean_all_rx_rings(struct igb_adapter *);
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static void igb_clean_all_rx_rings(struct igb_adapter *);
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@@ -1101,8 +1102,10 @@ static void igb_configure(struct igb_adapter *adapter)
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igb_restore_vlan(adapter);
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igb_restore_vlan(adapter);
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igb_configure_tx(adapter);
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igb_setup_tctl(adapter);
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igb_setup_rctl(adapter);
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igb_setup_rctl(adapter);
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igb_configure_tx(adapter);
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igb_configure_rx(adapter);
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igb_configure_rx(adapter);
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igb_rx_fifo_flush_82575(&adapter->hw);
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igb_rx_fifo_flush_82575(&adapter->hw);
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@@ -2069,48 +2072,15 @@ static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
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}
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}
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/**
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/**
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* igb_configure_tx - Configure transmit Unit after Reset
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* igb_setup_tctl - configure the transmit control registers
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* @adapter: board private structure
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* @adapter: Board private structure
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*
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* Configure the Tx unit of the MAC after a reset.
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**/
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**/
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static void igb_configure_tx(struct igb_adapter *adapter)
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static void igb_setup_tctl(struct igb_adapter *adapter)
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{
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{
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u64 tdba;
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struct e1000_hw *hw = &adapter->hw;
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struct e1000_hw *hw = &adapter->hw;
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u32 tctl;
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u32 tctl;
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u32 txdctl, txctrl;
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int i, j;
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for (i = 0; i < adapter->num_tx_queues; i++) {
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/* disable queue 0 which is enabled by default on 82575 and 82576 */
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struct igb_ring *ring = &adapter->tx_ring[i];
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j = ring->reg_idx;
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wr32(E1000_TDLEN(j),
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ring->count * sizeof(union e1000_adv_tx_desc));
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tdba = ring->dma;
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wr32(E1000_TDBAL(j),
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tdba & 0x00000000ffffffffULL);
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wr32(E1000_TDBAH(j), tdba >> 32);
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ring->head = E1000_TDH(j);
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ring->tail = E1000_TDT(j);
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writel(0, hw->hw_addr + ring->tail);
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writel(0, hw->hw_addr + ring->head);
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txdctl = rd32(E1000_TXDCTL(j));
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txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
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wr32(E1000_TXDCTL(j), txdctl);
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/* Turn off Relaxed Ordering on head write-backs. The
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* writebacks MUST be delivered in order or it will
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* completely screw up our bookeeping.
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*/
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txctrl = rd32(E1000_DCA_TXCTRL(j));
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txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
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wr32(E1000_DCA_TXCTRL(j), txctrl);
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}
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/* disable queue 0 to prevent tail bump w/o re-configuration */
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if (adapter->vfs_allocated_count)
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wr32(E1000_TXDCTL(0), 0);
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wr32(E1000_TXDCTL(0), 0);
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/* Program the Transmit Control Register */
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/* Program the Transmit Control Register */
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@@ -2121,15 +2091,70 @@ static void igb_configure_tx(struct igb_adapter *adapter)
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igb_config_collision_dist(hw);
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igb_config_collision_dist(hw);
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/* Setup Transmit Descriptor Settings for eop descriptor */
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adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
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/* Enable transmits */
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/* Enable transmits */
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tctl |= E1000_TCTL_EN;
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tctl |= E1000_TCTL_EN;
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wr32(E1000_TCTL, tctl);
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wr32(E1000_TCTL, tctl);
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}
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}
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/**
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* igb_configure_tx_ring - Configure transmit ring after Reset
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* @adapter: board private structure
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* @ring: tx ring to configure
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*
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* Configure a transmit ring after a reset.
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**/
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static void igb_configure_tx_ring(struct igb_adapter *adapter,
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struct igb_ring *ring)
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{
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struct e1000_hw *hw = &adapter->hw;
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u32 txdctl;
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u64 tdba = ring->dma;
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int reg_idx = ring->reg_idx;
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/* disable the queue */
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txdctl = rd32(E1000_TXDCTL(reg_idx));
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wr32(E1000_TXDCTL(reg_idx),
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txdctl & ~E1000_TXDCTL_QUEUE_ENABLE);
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wrfl();
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mdelay(10);
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wr32(E1000_TDLEN(reg_idx),
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ring->count * sizeof(union e1000_adv_tx_desc));
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wr32(E1000_TDBAL(reg_idx),
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tdba & 0x00000000ffffffffULL);
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wr32(E1000_TDBAH(reg_idx), tdba >> 32);
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ring->head = E1000_TDH(reg_idx);
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ring->tail = E1000_TDT(reg_idx);
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writel(0, hw->hw_addr + ring->tail);
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writel(0, hw->hw_addr + ring->head);
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txdctl |= IGB_TX_PTHRESH;
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txdctl |= IGB_TX_HTHRESH << 8;
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txdctl |= IGB_TX_WTHRESH << 16;
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txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
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wr32(E1000_TXDCTL(reg_idx), txdctl);
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}
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/**
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* igb_configure_tx - Configure transmit Unit after Reset
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* @adapter: board private structure
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*
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* Configure the Tx unit of the MAC after a reset.
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**/
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static void igb_configure_tx(struct igb_adapter *adapter)
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{
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int i;
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for (i = 0; i < adapter->num_tx_queues; i++)
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igb_configure_tx_ring(adapter, &adapter->tx_ring[i]);
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/* Setup Transmit Descriptor Settings for eop descriptor */
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adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
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}
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/**
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/**
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* igb_setup_rx_resources - allocate Rx resources (Descriptors)
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* igb_setup_rx_resources - allocate Rx resources (Descriptors)
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* @adapter: board private structure
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* @adapter: board private structure
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@@ -2333,6 +2358,49 @@ static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
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wr32(E1000_VT_CTL, vtctl);
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wr32(E1000_VT_CTL, vtctl);
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}
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}
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/**
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* igb_configure_rx_ring - Configure a receive ring after Reset
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* @adapter: board private structure
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* @ring: receive ring to be configured
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*
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* Configure the Rx unit of the MAC after a reset.
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**/
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static void igb_configure_rx_ring(struct igb_adapter *adapter,
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struct igb_ring *ring)
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{
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struct e1000_hw *hw = &adapter->hw;
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u64 rdba = ring->dma;
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int reg_idx = ring->reg_idx;
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u32 rxdctl;
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/* disable the queue */
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rxdctl = rd32(E1000_RXDCTL(reg_idx));
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wr32(E1000_RXDCTL(reg_idx),
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rxdctl & ~E1000_RXDCTL_QUEUE_ENABLE);
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/* Set DMA base address registers */
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wr32(E1000_RDBAL(reg_idx),
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rdba & 0x00000000ffffffffULL);
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wr32(E1000_RDBAH(reg_idx), rdba >> 32);
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wr32(E1000_RDLEN(reg_idx),
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ring->count * sizeof(union e1000_adv_rx_desc));
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/* initialize head and tail */
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ring->head = E1000_RDH(reg_idx);
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ring->tail = E1000_RDT(reg_idx);
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writel(0, hw->hw_addr + ring->head);
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writel(0, hw->hw_addr + ring->tail);
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/* enable receive descriptor fetching */
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rxdctl = rd32(E1000_RXDCTL(reg_idx));
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rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
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rxdctl &= 0xFFF00000;
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rxdctl |= IGB_RX_PTHRESH;
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rxdctl |= IGB_RX_HTHRESH << 8;
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rxdctl |= IGB_RX_WTHRESH << 16;
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wr32(E1000_RXDCTL(reg_idx), rxdctl);
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}
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/**
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/**
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* igb_configure_rx - Configure receive Unit after Reset
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* igb_configure_rx - Configure receive Unit after Reset
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* @adapter: board private structure
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* @adapter: board private structure
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@@ -2341,10 +2409,8 @@ static void igb_configure_vt_default_pool(struct igb_adapter *adapter)
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**/
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**/
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static void igb_configure_rx(struct igb_adapter *adapter)
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static void igb_configure_rx(struct igb_adapter *adapter)
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{
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{
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u64 rdba;
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struct e1000_hw *hw = &adapter->hw;
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struct e1000_hw *hw = &adapter->hw;
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u32 rctl, rxcsum;
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u32 rctl, rxcsum;
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u32 rxdctl;
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int i;
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int i;
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/* disable receives while setting up the descriptors */
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/* disable receives while setting up the descriptors */
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@@ -2358,29 +2424,8 @@ static void igb_configure_rx(struct igb_adapter *adapter)
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/* Setup the HW Rx Head and Tail Descriptor Pointers and
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/* Setup the HW Rx Head and Tail Descriptor Pointers and
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* the Base and Length of the Rx Descriptor Ring */
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* the Base and Length of the Rx Descriptor Ring */
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for (i = 0; i < adapter->num_rx_queues; i++) {
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for (i = 0; i < adapter->num_rx_queues; i++)
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struct igb_ring *ring = &adapter->rx_ring[i];
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igb_configure_rx_ring(adapter, &adapter->rx_ring[i]);
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int j = ring->reg_idx;
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rdba = ring->dma;
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wr32(E1000_RDBAL(j),
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rdba & 0x00000000ffffffffULL);
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wr32(E1000_RDBAH(j), rdba >> 32);
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wr32(E1000_RDLEN(j),
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ring->count * sizeof(union e1000_adv_rx_desc));
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ring->head = E1000_RDH(j);
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ring->tail = E1000_RDT(j);
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writel(0, hw->hw_addr + ring->tail);
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writel(0, hw->hw_addr + ring->head);
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rxdctl = rd32(E1000_RXDCTL(j));
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rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
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rxdctl &= 0xFFF00000;
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rxdctl |= IGB_RX_PTHRESH;
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rxdctl |= IGB_RX_HTHRESH << 8;
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rxdctl |= IGB_RX_WTHRESH << 16;
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wr32(E1000_RXDCTL(j), rxdctl);
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}
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if (adapter->num_rx_queues > 1) {
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if (adapter->num_rx_queues > 1) {
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u32 random[10];
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u32 random[10];
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