lk/linux-kernel-test
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

[MIPS] Fix build for PNX platforms.

Browse Source 
Build error was caused by commit 351336929c.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2008-06-12 17:26:02 +01:00
parent 330117ff27
commit 89052bd7b3
4 changed files with 28 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

26
arch/mips/mm/c-r4k.c
View File

@@ -1226,6 +1226,28 @@ void au1x00_fixup_config_od(void)
} }
} }
/* CP0 hazard avoidance. */
#define NXP_BARRIER() \
__asm__ __volatile__( \
".set noreorder\n\t" \
"nop; nop; nop; nop; nop; nop;\n\t" \
".set reorder\n\t")
static void nxp_pr4450_fixup_config(void)
{
unsigned long config0;
config0 = read_c0_config();
/* clear all three cache coherency fields */
config0 &= ~(0x7 | (7 << 25) | (7 << 28));
config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
((_page_cachable_default >> _CACHE_SHIFT) << 25) |
((_page_cachable_default >> _CACHE_SHIFT) << 28));
write_c0_config(config0);
NXP_BARRIER();
}
static int __cpuinitdata cca = -1; static int __cpuinitdata cca = -1;
static int __init cca_setup(char *str) static int __init cca_setup(char *str)
@@ -1271,6 +1293,10 @@ static void __cpuinit coherency_setup(void)
case CPU_AU1500: /* rev. AB */ case CPU_AU1500: /* rev. AB */
au1x00_fixup_config_od(); au1x00_fixup_config_od();
break; break;
case PRID_IMP_PR4450:
nxp_pr4450_fixup_config();
break;
} }
} }

11
arch/mips/nxp/pnx8550/jbs/board_setup.c
View File

@@ -47,16 +47,7 @@
void __init board_setup(void) void __init board_setup(void)
{ {
unsigned long config0, configpr; unsigned long configpr;
config0 = read_c0_config();
/* clear all three cache coherency fields */
config0 &= ~(0x7 | (7<<25) | (7<<28));
config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
(CONF_CM_DEFAULT<<28));
write_c0_config(config0);
BARRIER;
configpr = read_c0_config7(); configpr = read_c0_config7();
configpr |= (1<<19); /* enable tlb */ configpr |= (1<<19); /* enable tlb */

10
arch/mips/nxp/pnx8550/stb810/board_setup.c
View File

@@ -33,15 +33,7 @@
void __init board_setup(void) void __init board_setup(void)
{ {
unsigned long config0, configpr; unsigned long configpr;
config0 = read_c0_config();
/* clear all three cache coherency fields */
config0 &= ~(0x7 | (7<<25) | (7<<28));
config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) |
(CONF_CM_DEFAULT<<28));
write_c0_config(config0);
configpr = read_c0_config7(); configpr = read_c0_config7();
configpr |= (1<<19); /* enable tlb */ configpr |= (1<<19); /* enable tlb */

2
include/asm-mips/pgtable-bits.h
View File

@@ -134,6 +134,4 @@
#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
#define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT>>_CACHE_SHIFT)
#endif /* _ASM_PGTABLE_BITS_H */ #endif /* _ASM_PGTABLE_BITS_H */