lk/linux-kernel-test
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merge master.kernel.org:/home/rmk/linux-2.6-arm

Browse Source 
* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 3533/1: Implement the __raw_(read|write)_can_lock functions on ARM
  [ARM] 3530/1: PXA Mainstone: prevent double enable_irq() in pcmcia
  [ARM] 3529/1: s3c24xx: fix restoring control register with undefined instruction
This commit is contained in:
Linus Torvalds
2006-05-19 16:42:11 -07:00
parent b0c51b7d65 c2a4c40651
commit 890f74291c
3 changed files with 12 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/mach-pxa/mainstone.c
View File

@@ -95,7 +95,10 @@ static void __init mainstone_init_irq(void)
for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
set_irq_chip(irq, &mainstone_irq_chip); set_irq_chip(irq, &mainstone_irq_chip);
set_irq_handler(irq, do_level_IRQ); set_irq_handler(irq, do_level_IRQ);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
else
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
set_irq_flags(MAINSTONE_IRQ(8), 0); set_irq_flags(MAINSTONE_IRQ(8), 0);
set_irq_flags(MAINSTONE_IRQ(12), 0); set_irq_flags(MAINSTONE_IRQ(12), 0);

6
arch/arm/mach-s3c2410/sleep.S
View File

@@ -59,8 +59,7 @@ ENTRY(s3c2410_cpu_suspend)
mrc p15, 0, r5, c13, c0, 0 @ PID mrc p15, 0, r5, c13, c0, 0 @ PID
mrc p15, 0, r6, c3, c0, 0 @ Domain ID mrc p15, 0, r6, c3, c0, 0 @ Domain ID
mrc p15, 0, r7, c2, c0, 0 @ translation table base address mrc p15, 0, r7, c2, c0, 0 @ translation table base address
mrc p15, 0, r8, c2, c0, 0 @ auxiliary control register mrc p15, 0, r8, c1, c0, 0 @ control register
mrc p15, 0, r9, c1, c0, 0 @ control register
stmia r0, { r4 - r13 } stmia r0, { r4 - r13 }
@@ -165,7 +164,6 @@ ENTRY(s3c2410_cpu_resume)
mcr p15, 0, r5, c13, c0, 0 @ PID mcr p15, 0, r5, c13, c0, 0 @ PID
mcr p15, 0, r6, c3, c0, 0 @ Domain ID mcr p15, 0, r6, c3, c0, 0 @ Domain ID
mcr p15, 0, r7, c2, c0, 0 @ translation table base mcr p15, 0, r7, c2, c0, 0 @ translation table base
mcr p15, 0, r8, c1, c1, 0 @ auxilliary control
#ifdef CONFIG_DEBUG_RESUME #ifdef CONFIG_DEBUG_RESUME
mov r3, #'R' mov r3, #'R'
@@ -173,7 +171,7 @@ ENTRY(s3c2410_cpu_resume)
#endif #endif
ldr r2, =resume_with_mmu ldr r2, =resume_with_mmu
mcr p15, 0, r9, c1, c0, 0 @ turn on MMU, etc mcr p15, 0, r8, c1, c0, 0 @ turn on MMU, etc
nop @ second-to-last before mmu nop @ second-to-last before mmu
mov pc, r2 @ go back to virtual address mov pc, r2 @ go back to virtual address

6
include/asm-arm/spinlock.h
View File

@@ -142,6 +142,9 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
: "cc"); : "cc");
} }
/* write_can_lock - would write_trylock() succeed? */
#define __raw_write_can_lock(x) ((x)->lock == 0x80000000)
/* /*
* Read locks are a bit more hairy: * Read locks are a bit more hairy:
* - Exclusively load the lock value. * - Exclusively load the lock value.
@@ -198,4 +201,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
#define __raw_read_trylock(lock) generic__raw_read_trylock(lock) #define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
/* read_can_lock - would read_trylock() succeed? */
#define __raw_read_can_lock(x) ((x)->lock < 0x80000000)
#endif /* __ASM_SPINLOCK_H */ #endif /* __ASM_SPINLOCK_H */