m68knommu: fix problems with SPI/GPIO on ColdFire 520x
The problem has its root in the calculation of the set-port offsets (macro MCFGPIO_SETR() in arch/m68k/include/asm/gpio.h), this assumes that all ports have the same offset from the base port address (MCFGPIO_SETR) which is defined in mcf520xsim.h as an alias of MCFGIO_PSETR_BUSCTL. Because the BUSCTL and BE port do not have a set-register (see MCF5208 Reference Manual Page 13-10, Table 13-3) the offset calculations went wrong. Because the BE and BUSCTL port do not seem useful in these parts, as they lack a set register, I removed them and adapted the gpio chip bases which are also used for the offset-calculations. Now both setting and resetting the chip selects works as expected from userland and from the kernelspace. Signed-off-by: Peter Turczak <peter@turczak.de> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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committed by
Greg Ungerer
parent
f230e80b42
commit
89127ed381
@@ -24,9 +24,11 @@
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#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
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#define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340)
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#elif defined(CONFIG_M5249)
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#define MCFQSPI_IOBASE (MCF_MBAR + 0x300)
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#elif defined(CONFIG_M520x) || defined(CONFIG_M532x)
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#define MCFQSPI_IOBASE 0xFC058000
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#define MCFQSPI_IOBASE (MCF_MBAR + 0x300)
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#elif defined(CONFIG_M520x)
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#define MCFQSPI_IOBASE 0xFC05C000
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#elif defined(CONFIG_M532x)
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#define MCFQSPI_IOBASE 0xFC058000
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#endif
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#define MCFQSPI_IOSIZE 0x40
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