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timbgpio: add support for interrupt triggering on both flanks

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Introduce support for triggering interrupts on both rising and falling
edge.

This feature requires version 3 or newer of the IP, a version check is
done when triggering on both edges is requested.

Signed-off-by: Richard Röjfors <richard.rojfors@pelagicore.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Richard Röjfors
2010-03-05 13:44:35 -08:00
committed by Linus Torvalds
parent 3e45f1d115
commit 8c35c89aa3
1 changed files with 23 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
drivers/gpio/timbgpio.c
View File

@@ -38,6 +38,8 @@
#define TGPIO_ICR 0x14 #define TGPIO_ICR 0x14
#define TGPIO_FLR 0x18 #define TGPIO_FLR 0x18
#define TGPIO_LVR 0x1c #define TGPIO_LVR 0x1c
#define TGPIO_VER 0x20
#define TGPIO_BFLR 0x24
struct timbgpio { struct timbgpio {
void __iomem *membase; void __iomem *membase;
@@ -126,17 +128,23 @@ static int timbgpio_irq_type(unsigned irq, unsigned trigger)
struct timbgpio *tgpio = get_irq_chip_data(irq); struct timbgpio *tgpio = get_irq_chip_data(irq);
int offset = irq - tgpio->irq_base; int offset = irq - tgpio->irq_base;
unsigned long flags; unsigned long flags;
u32 lvr, flr; u32 lvr, flr, bflr = 0;
u32 ver;
if (offset < 0 || offset > tgpio->gpio.ngpio) if (offset < 0 || offset > tgpio->gpio.ngpio)
return -EINVAL; return -EINVAL;
ver = ioread32(tgpio->membase + TGPIO_VER);
spin_lock_irqsave(&tgpio->lock, flags); spin_lock_irqsave(&tgpio->lock, flags);
lvr = ioread32(tgpio->membase + TGPIO_LVR); lvr = ioread32(tgpio->membase + TGPIO_LVR);
flr = ioread32(tgpio->membase + TGPIO_FLR); flr = ioread32(tgpio->membase + TGPIO_FLR);
if (ver > 2)
bflr = ioread32(tgpio->membase + TGPIO_BFLR);
if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
bflr &= ~(1 << offset);
flr &= ~(1 << offset); flr &= ~(1 << offset);
if (trigger & IRQ_TYPE_LEVEL_HIGH) if (trigger & IRQ_TYPE_LEVEL_HIGH)
lvr |= 1 << offset; lvr |= 1 << offset;
@@ -144,21 +152,27 @@ static int timbgpio_irq_type(unsigned irq, unsigned trigger)
lvr &= ~(1 << offset); lvr &= ~(1 << offset);
} }
if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
if (ver < 3)
return -EINVAL; return -EINVAL;
else { else {
flr |= 1 << offset; flr |= 1 << offset;
/* opposite compared to the datasheet, but it mirrors the bflr |= 1 << offset;
* reality }
*/ } else {
bflr &= ~(1 << offset);
flr |= 1 << offset;
if (trigger & IRQ_TYPE_EDGE_FALLING) if (trigger & IRQ_TYPE_EDGE_FALLING)
lvr |= 1 << offset;
else
lvr &= ~(1 << offset); lvr &= ~(1 << offset);
else
lvr |= 1 << offset;
} }
iowrite32(lvr, tgpio->membase + TGPIO_LVR); iowrite32(lvr, tgpio->membase + TGPIO_LVR);
iowrite32(flr, tgpio->membase + TGPIO_FLR); iowrite32(flr, tgpio->membase + TGPIO_FLR);
if (ver > 2)
iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
iowrite32(1 << offset, tgpio->membase + TGPIO_ICR); iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
spin_unlock_irqrestore(&tgpio->lock, flags); spin_unlock_irqrestore(&tgpio->lock, flags);