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arm/imx: remove imx_idle hook and use pm_idle instead

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The patch removes imx_idle hook and use pm_idle instead to get imx
arch_idle prepared for the cleanup.  It's suggested by Russel King
as below.

> The final removal of mach/system.h depends on getting rid of the arch_idle
> thing.  While going through these headers, I was dismayed to find these:
>
> arch/arm/mach-s3c2410/include/mach/system.h:void (*s3c24xx_idle)(void);
> arch/arm/plat-mxc/include/mach/system.h:extern void (*imx_idle)(void);
>
> when we have a perfectly good pm_idle hook already in place - so there's
> no excuse for these especially when other platforms are already using
> pm_idle to hook their platform specific idle function into.  This is
> something that better be gone at the next merge window!

Suggested-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Shawn Guo
2011-11-11 13:09:18 +08:00
committed by Sascha Hauer
parent 6a53fc531d
commit 8c6d8319ec
5 changed files with 33 additions and 35 deletions
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53
arch/arm/mach-imx/mm-imx3.c
View File

@@ -33,29 +33,32 @@
static void imx3_idle(void) static void imx3_idle(void)
{ {
unsigned long reg = 0; unsigned long reg = 0;
__asm__ __volatile__(
/* disable I and D cache */ if (!need_resched())
"mrc p15, 0, %0, c1, c0, 0\n" __asm__ __volatile__(
"bic %0, %0, #0x00001000\n" /* disable I and D cache */
"bic %0, %0, #0x00000004\n" "mrc p15, 0, %0, c1, c0, 0\n"
"mcr p15, 0, %0, c1, c0, 0\n" "bic %0, %0, #0x00001000\n"
/* invalidate I cache */ "bic %0, %0, #0x00000004\n"
"mov %0, #0\n" "mcr p15, 0, %0, c1, c0, 0\n"
"mcr p15, 0, %0, c7, c5, 0\n" /* invalidate I cache */
/* clear and invalidate D cache */ "mov %0, #0\n"
"mov %0, #0\n" "mcr p15, 0, %0, c7, c5, 0\n"
"mcr p15, 0, %0, c7, c14, 0\n" /* clear and invalidate D cache */
/* WFI */ "mov %0, #0\n"
"mov %0, #0\n" "mcr p15, 0, %0, c7, c14, 0\n"
"mcr p15, 0, %0, c7, c0, 4\n" /* WFI */
"nop\n" "nop\n" "nop\n" "nop\n" "mov %0, #0\n"
"nop\n" "nop\n" "nop\n" "mcr p15, 0, %0, c7, c0, 4\n"
/* enable I and D cache */ "nop\n" "nop\n" "nop\n" "nop\n"
"mrc p15, 0, %0, c1, c0, 0\n" "nop\n" "nop\n" "nop\n"
"orr %0, %0, #0x00001000\n" /* enable I and D cache */
"orr %0, %0, #0x00000004\n" "mrc p15, 0, %0, c1, c0, 0\n"
"mcr p15, 0, %0, c1, c0, 0\n" "orr %0, %0, #0x00001000\n"
: "=r" (reg)); "orr %0, %0, #0x00000004\n"
"mcr p15, 0, %0, c1, c0, 0\n"
: "=r" (reg));
local_irq_enable();
} }
static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size, static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
@@ -143,7 +146,7 @@ void __init imx31_init_early(void)
{ {
mxc_set_cpu_type(MXC_CPU_MX31); mxc_set_cpu_type(MXC_CPU_MX31);
mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR)); mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
imx_idle = imx3_idle; pm_idle = imx3_idle;
imx_ioremap = imx3_ioremap; imx_ioremap = imx3_ioremap;
} }
@@ -152,7 +155,7 @@ void __init imx35_init_early(void)
mxc_set_cpu_type(MXC_CPU_MX35); mxc_set_cpu_type(MXC_CPU_MX35);
mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR)); mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
imx_idle = imx3_idle; pm_idle = imx3_idle;
imx_ioremap = imx3_ioremap; imx_ioremap = imx3_ioremap;
} }

6
arch/arm/mach-mx5/mm.c
View File

@@ -23,7 +23,9 @@
static void imx5_idle(void) static void imx5_idle(void)
{ {
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); if (!need_resched())
mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
local_irq_enable();
} }
/* /*
@@ -89,7 +91,7 @@ void __init imx51_init_early(void)
mxc_set_cpu_type(MXC_CPU_MX51); mxc_set_cpu_type(MXC_CPU_MX51);
mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
imx_idle = imx5_idle; pm_idle = imx5_idle;
} }
void __init imx53_init_early(void) void __init imx53_init_early(void)

1
arch/arm/plat-mxc/include/mach/common.h
View File

@@ -85,7 +85,6 @@ enum mxc_cpu_pwr_mode {
}; };
extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode); extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
extern void (*imx_idle)(void);
extern void imx_print_silicon_rev(const char *cpu, int srev); extern void imx_print_silicon_rev(const char *cpu, int srev);
void avic_handle_irq(struct pt_regs *); void avic_handle_irq(struct pt_regs *);

7
arch/arm/plat-mxc/include/mach/system.h
View File

@@ -17,14 +17,9 @@
#ifndef __ASM_ARCH_MXC_SYSTEM_H__ #ifndef __ASM_ARCH_MXC_SYSTEM_H__
#define __ASM_ARCH_MXC_SYSTEM_H__ #define __ASM_ARCH_MXC_SYSTEM_H__
extern void (*imx_idle)(void);
static inline void arch_idle(void) static inline void arch_idle(void)
{ {
if (imx_idle != NULL) cpu_do_idle();
(imx_idle)();
else
cpu_do_idle();
} }
void arch_reset(char mode, const char *cmd); void arch_reset(char mode, const char *cmd);

1
arch/arm/plat-mxc/system.c
View File

@@ -28,7 +28,6 @@
#include <asm/system.h> #include <asm/system.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
void (*imx_idle)(void) = NULL;
void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL; void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
static void __iomem *wdog_base; static void __iomem *wdog_base;