drm/i915: scramble reset support for DP port CRC on vlv
They've moved the DC balance reset bit around. Again I don't think we need it, but better safe than sorry and maybe HDMI port CRC will prove useful for checking infoframes or hdmi audio. v2: Apply the suggestions from Damien's review. Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@@ -2026,6 +2026,9 @@ static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
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enum intel_pipe_crc_source *source,
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enum intel_pipe_crc_source *source,
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uint32_t *val)
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uint32_t *val)
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{
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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bool need_stable_symbols = false;
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if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
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if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
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int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
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int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
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if (ret)
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if (ret)
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@@ -2038,9 +2041,11 @@ static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
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break;
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break;
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case INTEL_PIPE_CRC_SOURCE_DP_B:
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case INTEL_PIPE_CRC_SOURCE_DP_B:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
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need_stable_symbols = true;
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break;
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break;
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case INTEL_PIPE_CRC_SOURCE_DP_C:
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case INTEL_PIPE_CRC_SOURCE_DP_C:
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
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*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
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need_stable_symbols = true;
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break;
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break;
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case INTEL_PIPE_CRC_SOURCE_NONE:
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case INTEL_PIPE_CRC_SOURCE_NONE:
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*val = 0;
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*val = 0;
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@@ -2049,6 +2054,29 @@ static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
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return -EINVAL;
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return -EINVAL;
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}
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}
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/*
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* When the pipe CRC tap point is after the transcoders we need
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* to tweak symbol-level features to produce a deterministic series of
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* symbols for a given frame. We need to reset those features only once
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* a frame (instead of every nth symbol):
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* - DC-balance: used to ensure a better clock recovery from the data
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* link (SDVO)
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* - DisplayPort scrambling: used for EMI reduction
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*/
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if (need_stable_symbols) {
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uint32_t tmp = I915_READ(PORT_DFT2_G4X);
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WARN_ON(!IS_G4X(dev));
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tmp |= DC_BALANCE_RESET_VLV;
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if (pipe == PIPE_A)
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tmp |= PIPE_A_SCRAMBLE_RESET;
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else
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tmp |= PIPE_B_SCRAMBLE_RESET;
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I915_WRITE(PORT_DFT2_G4X, tmp);
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}
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return 0;
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return 0;
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}
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}
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@@ -2128,6 +2156,22 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
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return 0;
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return 0;
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}
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}
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static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
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enum pipe pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t tmp = I915_READ(PORT_DFT2_G4X);
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if (pipe == PIPE_A)
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tmp &= ~PIPE_A_SCRAMBLE_RESET;
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else
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tmp &= ~PIPE_B_SCRAMBLE_RESET;
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if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
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tmp &= ~DC_BALANCE_RESET_VLV;
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I915_WRITE(PORT_DFT2_G4X, tmp);
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}
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static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
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static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
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enum pipe pipe)
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enum pipe pipe)
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{
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{
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@@ -2267,6 +2311,8 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
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if (IS_G4X(dev))
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if (IS_G4X(dev))
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g4x_undo_pipe_scramble_reset(dev, pipe);
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g4x_undo_pipe_scramble_reset(dev, pipe);
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else if (IS_VALLEYVIEW(dev))
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vlv_undo_pipe_scramble_reset(dev, pipe);
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}
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}
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return 0;
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return 0;
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