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perf, x86: Clean up IA32_PERF_CAPABILITIES usage

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Saner PERF_CAPABILITIES support, which also exposes pebs_trap. Use that
latter to make PEBS's use of LBR conditional since a fault-like pebs
should already report the correct IP.

( As of this writing there is no known hardware that implements
  !pebs_trap )

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <20100304140100.770650663@chello.nl>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Peter Zijlstra
2010-03-03 17:07:40 +01:00
committed by Ingo Molnar
parent 1676b8a077
commit 8db909a7e3
4 changed files with 42 additions and 31 deletions
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15
arch/x86/kernel/cpu/perf_event.c
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@ -154,6 +154,17 @@ struct cpu_hw_events {
#define for_each_event_constraint(e, c) \
for ((e) = (c); (e)->cmask; (e)++)
union perf_capabilities {
struct {
u64 lbr_format : 6;
u64 pebs_trap : 1;
u64 pebs_arch_reg : 1;
u64 pebs_format : 4;
u64 smm_freeze : 1;
};
u64 capabilities;
};
/*
* struct x86_pmu - generic x86 pmu
*/
@ -195,7 +206,8 @@ struct x86_pmu {
/*
* Intel Arch Perfmon v2+
*/
u64 intel_ctrl;
u64 intel_ctrl;
union perf_capabilities intel_cap;
/*
* Intel DebugStore bits
@ -210,7 +222,6 @@ struct x86_pmu {
*/
unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
int lbr_nr; /* hardware stack size */
int lbr_format; /* hardware format */
};
static struct x86_pmu x86_pmu __read_mostly;