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[AVR32] Clean up OCD register usage

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Generate a new set of OCD register definitions in asm/ocd.h and rename
__mfdr() and __mtdr() to ocd_read() and ocd_write() respectively.

The bitfield definitions are a lot more complete now, and they are
entirely based on bit numbers, not masks. This is because OCD
registers are frequently accessed from assembly code, where bit
numbers are a lot more useful (can be fed directly to sbr, bfins,
etc.)

Bitfields that consist of more than one bit have two definitions:
_START, which indicates the number of the first bit, and _SIZE, which
indicates the number of bits. These directly correspond to the
parameters taken by the bfextu, bfexts and bfins instructions.

Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
This commit is contained in:
Haavard Skinnemoen
2007-11-27 13:31:20 +01:00
parent 320516b78b
commit 8dfe8f29cd
7 changed files with 557 additions and 95 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
arch/avr32/kernel/entry-avr32b.S
View File

@@ -270,8 +270,8 @@ syscall_exit_work:
lsl r3, 1
sbr r3, 30
sbr r3, 0
mtdr DBGREG_BWA2A, r2
mtdr DBGREG_BWC2A, r3
mtdr OCD_BWA2A, r2
mtdr OCD_BWC2A, r3
rjmp syscall_exit_cont
@@ -521,8 +521,8 @@ fault_exit_work:
lsl r3, 1
sbr r3, 30
sbr r3, 0
mtdr DBGREG_BWA2A, r2
mtdr DBGREG_BWC2A, r3
mtdr OCD_BWA2A, r2
mtdr OCD_BWC2A, r3
rjmp fault_resume_user
/* If we get a debug trap from privileged context we end up here */
@@ -636,9 +636,9 @@ debug_resume_user:
3: bld r1, TIF_SINGLE_STEP
brcc debug_restore_all
mfdr r2, DBGREG_DC
sbr r2, DC_SS_BIT
mtdr DBGREG_DC, r2
mfdr r2, OCD_DC
sbr r2, OCD_DC_SS_BIT
mtdr OCD_DC, r2
rjmp debug_restore_all
.set rsr_int0, SYSREG_RSR_INT0

14
arch/avr32/kernel/kprobes.c
View File

@@ -70,9 +70,9 @@ static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
BUG_ON(!(sysreg_read(SR) & SYSREG_BIT(SR_D)));
dc = __mfdr(DBGREG_DC);
dc |= DC_SS;
__mtdr(DBGREG_DC, dc);
dc = ocd_read(DC);
dc |= 1 << OCD_DC_SS_BIT;
ocd_write(DC, dc);
/*
* We must run the instruction from its original location
@@ -91,9 +91,9 @@ static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs)
pr_debug("resuming execution at PC=%08lx\n", regs->pc);
dc = __mfdr(DBGREG_DC);
dc &= ~DC_SS;
__mtdr(DBGREG_DC, dc);
dc = ocd_read(DC);
dc &= ~(1 << OCD_DC_SS_BIT);
ocd_write(DC, dc);
*p->addr = BREAKPOINT_INSTRUCTION;
flush_icache_range((unsigned long)p->addr,
@@ -261,7 +261,7 @@ int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
int __init arch_init_kprobes(void)
{
printk("KPROBES: Enabling monitor mode (MM|DBE)...\n");
__mtdr(DBGREG_DC, DC_MM | DC_DBE);
ocd_write(DC, (1 << OCD_DC_MM_BIT) | (1 << OCD_DC_DBE_BIT));
/* TODO: Register kretprobe trampoline */
return 0;

4
arch/avr32/kernel/process.c
View File

@@ -55,8 +55,8 @@ void machine_power_off(void)
void machine_restart(char *cmd)
{
__mtdr(DBGREG_DC, DC_DBE);
__mtdr(DBGREG_DC, DC_RES);
ocd_write(DC, (1 << OCD_DC_DBE_BIT));
ocd_write(DC, (1 << OCD_DC_RES_BIT));
while (1) ;
}

34
arch/avr32/kernel/ptrace.c
View File

@@ -159,7 +159,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
request, child->pid, addr, data);
pr_debug("ptrace: Enabling monitor mode...\n");
__mtdr(DBGREG_DC, __mfdr(DBGREG_DC) | DC_MM | DC_DBE);
ocd_write(DC, ocd_read(DC) | (1 << OCD_DC_MM_BIT)
| (1 << OCD_DC_DBE_BIT));
switch (request) {
/* Read the word at location addr in the child process */
@@ -240,7 +241,8 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
break;
}
pr_debug("sys_ptrace returning %d (DC = 0x%08lx)\n", ret, __mfdr(DBGREG_DC));
pr_debug("sys_ptrace returning %d (DC = 0x%08lx)\n",
ret, ocd_read(DC));
return ret;
}
@@ -276,11 +278,11 @@ asmlinkage void do_debug_priv(struct pt_regs *regs)
unsigned long dc, ds;
unsigned long die_val;
ds = __mfdr(DBGREG_DS);
ds = ocd_read(DS);
pr_debug("do_debug_priv: pc = %08lx, ds = %08lx\n", regs->pc, ds);
if (ds & DS_SSS)
if (ds & (1 << OCD_DS_SSS_BIT))
die_val = DIE_SSTEP;
else
die_val = DIE_BREAKPOINT;
@@ -288,14 +290,14 @@ asmlinkage void do_debug_priv(struct pt_regs *regs)
if (notify_die(die_val, "ptrace", regs, 0, 0, SIGTRAP) == NOTIFY_STOP)
return;
if (likely(ds & DS_SSS)) {
if (likely(ds & (1 << OCD_DS_SSS_BIT))) {
extern void itlb_miss(void);
extern void tlb_miss_common(void);
struct thread_info *ti;
dc = __mfdr(DBGREG_DC);
dc &= ~DC_SS;
__mtdr(DBGREG_DC, dc);
dc = ocd_read(DC);
dc &= ~(1 << OCD_DC_SS_BIT);
ocd_write(DC, dc);
ti = current_thread_info();
set_ti_thread_flag(ti, TIF_BREAKPOINT);
@@ -303,8 +305,8 @@ asmlinkage void do_debug_priv(struct pt_regs *regs)
/* The TLB miss handlers don't check thread flags */
if ((regs->pc >= (unsigned long)&itlb_miss)
&& (regs->pc <= (unsigned long)&tlb_miss_common)) {
__mtdr(DBGREG_BWA2A, sysreg_read(RAR_EX));
__mtdr(DBGREG_BWC2A, 0x40000001 | (get_asid() << 1));
ocd_write(BWA2A, sysreg_read(RAR_EX));
ocd_write(BWC2A, 0x40000001 | (get_asid() << 1));
}
/*
@@ -329,22 +331,22 @@ asmlinkage void do_debug(struct pt_regs *regs)
{
unsigned long dc, ds;
ds = __mfdr(DBGREG_DS);
ds = ocd_read(DS);
pr_debug("do_debug: pc = %08lx, ds = %08lx\n", regs->pc, ds);
if (test_thread_flag(TIF_BREAKPOINT)) {
pr_debug("TIF_BREAKPOINT set\n");
/* We're taking care of it */
clear_thread_flag(TIF_BREAKPOINT);
__mtdr(DBGREG_BWC2A, 0);
ocd_write(BWC2A, 0);
}
if (test_thread_flag(TIF_SINGLE_STEP)) {
pr_debug("TIF_SINGLE_STEP set, ds = 0x%08lx\n", ds);
if (ds & DS_SSS) {
dc = __mfdr(DBGREG_DC);
dc &= ~DC_SS;
__mtdr(DBGREG_DC, dc);
if (ds & (1 << OCD_DS_SSS_BIT)) {
dc = ocd_read(DC);
dc &= ~(1 << OCD_DC_SS_BIT);
ocd_write(DC, dc);
clear_thread_flag(TIF_SINGLE_STEP);
ptrace_break(current, regs);

2
arch/avr32/kernel/traps.c
View File

@@ -39,7 +39,7 @@ void NORET_TYPE die(const char *str, struct pt_regs *regs, long err)
printk("FRAME_POINTER ");
#endif
if (current_cpu_data.features & AVR32_FEATURE_OCD) {
unsigned long did = __mfdr(DBGREG_DID);
unsigned long did = ocd_read(DID);
printk("chip: 0x%03lx:0x%04lx rev %lu\n",
(did >> 1) & 0x7ff,
(did >> 12) & 0x7fff,