ARM: mm: Add strongly ordered descriptor support.
On certain architectures, there might be a need to mark certain addresses with strongly ordered memory attributes to avoid ordering issues at the interconnect level. On OMAP4, the asynchronous bridge buffers can only be drained with strongly ordered accesses and hence the need to mark the memory strongly ordered. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Woodruff Richard <r-woodruff2@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
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@@ -29,6 +29,7 @@ struct map_desc {
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#define MT_MEMORY_NONCACHED 11
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#define MT_MEMORY_DTCM 12
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#define MT_MEMORY_ITCM 13
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#define MT_MEMORY_SO 14
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#ifdef CONFIG_MMU
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extern void iotable_init(struct map_desc *, int);
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