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[MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers.

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
2007-10-11 23:46:09 +01:00
parent 90b02340dc
commit 91a2fcc886
11 changed files with 87 additions and 291 deletions
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72
arch/mips/mipssim/sim_time.c
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@@ -23,77 +23,6 @@
unsigned long cpu_khz;
irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
{
#ifdef CONFIG_SMP
int cpu = smp_processor_id();
/*
* CPU 0 handles the global timer interrupt job
* resets count/compare registers to trigger next timer int.
*/
#ifndef CONFIG_MIPS_MT_SMTC
if (cpu == 0) {
timer_interrupt(irq, dev_id);
} else {
/* Everyone else needs to reset the timer int here as
ll_local_timer_interrupt doesn't */
/*
* FIXME: need to cope with counter underflow.
* More support needs to be added to kernel/time for
* counter/timer interrupts on multiple CPU's
*/
write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
}
#else /* SMTC */
/*
* In SMTC system, one Count/Compare set exists per VPE.
* Which TC within a VPE gets the interrupt is essentially
* random - we only know that it shouldn't be one with
* IXMT set. Whichever TC gets the interrupt needs to
* send special interprocessor interrupts to the other
* TCs to make sure that they schedule, etc.
*
* That code is specific to the SMTC kernel, not to
* the simulation platform, so it's invoked from
* the general MIPS timer_interrupt routine.
*
* We have a problem in that the interrupt vector code
* had to turn off the timer IM bit to avoid redundant
* entries, but we may never get to mips_cpu_irq_end
* to turn it back on again if the scheduler gets
* involved. So we clear the pending timer here,
* and re-enable the mask...
*/
int vpflags = dvpe();
write_c0_compare (read_c0_count() - 1);
clear_c0_cause(0x100 << cp0_compare_irq);
set_c0_status(0x100 << cp0_compare_irq);
irq_enable_hazard();
evpe(vpflags);
if (cpu_data[cpu].vpe_id == 0)
timer_interrupt(irq, dev_id);
else
write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
smtc_timer_broadcast(cpu_data[cpu].vpe_id);
#endif /* CONFIG_MIPS_MT_SMTC */
/*
* every CPU should do profiling and process accounting
*/
local_timer_interrupt (irq, dev_id);
return IRQ_HANDLED;
#else
return timer_interrupt (irq, dev_id);
#endif
}
/*
* Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
*/
@@ -185,7 +114,6 @@ void __init plat_timer_setup(struct irqaction *irq)
}
/* we are using the cpu counter for timer interrupts */
irq->handler = sim_timer_interrupt;
setup_irq(mips_cpu_timer_irq, irq);
#ifdef CONFIG_SMP