[ARM] 2887/1: OMAP 2/4: Update files common to omap1 and omap2, take 2
Patch from Tony Lindgren This patch syncs the mainline kernel with linux-omap tree. The highlights of the patch are: - Clock updates by Tuukka Tikkanen, Juha Yrjola, Daniel Petrini and Tony Lindgren - DMA fixes by Imre Deak, Juha Yrjola and Daniel Petrini - Add support to dual-mode hardware timers by Lauri Leukkunen - GPIO support for 24xx by Paul Mundt - GPIO wake-up support by Tony Lindgren - Better GPIO interrupt handler to not lose interrupts by Ralph Walden and Ladislav Michl - Power Management updates by Tuukka Tikkanen - Make Power Management code use new SRAM functions by Tony Lindgren Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Tony Lindgren
committed by
Russell King
Russell King
parent
7efb833d64
commit
92105bb706
@@ -66,7 +66,7 @@ ENTRY(omap1510_idle_loop_suspend)
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@ get ARM_IDLECT2 into r2
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ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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mov r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
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orr r5,r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
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orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
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strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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@ request ARM idle
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@@ -76,7 +76,7 @@ ENTRY(omap1510_idle_loop_suspend)
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strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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mov r5, #IDLE_WAIT_CYCLES & 0xff
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orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
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orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
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l_1510: subs r5, r5, #1
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bne l_1510
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/*
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@@ -96,7 +96,7 @@ l_1510: subs r5, r5, #1
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strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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ldmfd sp!, {r0 - r12, pc} @ restore regs and return
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ldmfd sp!, {r0 - r12, pc} @ restore regs and return
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ENTRY(omap1510_idle_loop_suspend_sz)
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.word . - omap1510_idle_loop_suspend
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@@ -115,8 +115,8 @@ ENTRY(omap1610_idle_loop_suspend)
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@ turn off clock domains
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@ get ARM_IDLECT2 into r2
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ldrh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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mov r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff
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orr r5,r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff00
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mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
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orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
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strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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@ request ARM idle
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@@ -126,7 +126,7 @@ ENTRY(omap1610_idle_loop_suspend)
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strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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mov r5, #IDLE_WAIT_CYCLES & 0xff
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orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
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orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
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l_1610: subs r5, r5, #1
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bne l_1610
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/*
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@@ -146,7 +146,7 @@ l_1610: subs r5, r5, #1
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strh r2, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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strh r1, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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ldmfd sp!, {r0 - r12, pc} @ restore regs and return
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ldmfd sp!, {r0 - r12, pc} @ restore regs and return
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ENTRY(omap1610_idle_loop_suspend_sz)
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.word . - omap1610_idle_loop_suspend
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@@ -208,7 +208,7 @@ ENTRY(omap1510_cpu_suspend)
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@ turn off clock domains
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mov r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff
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orr r5,r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
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orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
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strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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@ request ARM idle
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@@ -217,7 +217,7 @@ ENTRY(omap1510_cpu_suspend)
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strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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mov r5, #IDLE_WAIT_CYCLES & 0xff
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orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
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orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
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l_1510_2:
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subs r5, r5, #1
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bne l_1510_2
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@@ -237,7 +237,7 @@ l_1510_2:
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strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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@ restore regs and return
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ldmfd sp!, {r0 - r12, pc}
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ldmfd sp!, {r0 - r12, pc}
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ENTRY(omap1510_cpu_suspend_sz)
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.word . - omap1510_cpu_suspend
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@@ -249,21 +249,26 @@ ENTRY(omap1610_cpu_suspend)
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@ save registers on stack
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stmfd sp!, {r0 - r12, lr}
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@ Drain write cache
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mov r4, #0
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mcr p15, 0, r0, c7, c10, 4
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nop
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@ load base address of Traffic Controller
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mov r4, #TCMIF_ASM_BASE & 0xff000000
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orr r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
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orr r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
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mov r6, #TCMIF_ASM_BASE & 0xff000000
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orr r6, r6, #TCMIF_ASM_BASE & 0x00ff0000
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orr r6, r6, #TCMIF_ASM_BASE & 0x0000ff00
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@ prepare to put SDRAM into self-refresh manually
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ldr r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
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orr r5, r5, #SELF_REFRESH_MODE & 0xff000000
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orr r5, r5, #SELF_REFRESH_MODE & 0x000000ff
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str r5, [r4, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
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ldr r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
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orr r9, r7, #SELF_REFRESH_MODE & 0xff000000
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orr r9, r9, #SELF_REFRESH_MODE & 0x000000ff
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str r9, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
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@ prepare to put EMIFS to Sleep
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ldr r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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orr r5, r5, #IDLE_EMIFS_REQUEST & 0xff
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str r5, [r4, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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ldr r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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orr r9, r8, #IDLE_EMIFS_REQUEST & 0xff
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str r9, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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@ load base address of ARM_IDLECT1 and ARM_IDLECT2
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mov r4, #CLKGEN_REG_ASM_BASE & 0xff000000
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@@ -271,26 +276,22 @@ ENTRY(omap1610_cpu_suspend)
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orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
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@ turn off clock domains
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mov r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff
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orr r5,r5, #OMAP1610_IDLE_CLOCK_DOMAINS & 0xff00
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strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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@ work around errata of OMAP1610/5912. Enable (!) peripheral
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@ clock to let the chip go into deep sleep
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ldrh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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orr r5,r5, #EN_PERCK_BIT & 0xff
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@ do not disable PERCK (0x04)
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mov r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff
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orr r5, r5, #OMAP1610_IDLECT2_SLEEP_VAL & 0xff00
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strh r5, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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@ request ARM idle
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mov r3, #OMAP1610_DEEP_SLEEP_REQUEST & 0xff
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orr r3, r3, #OMAP1610_DEEP_SLEEP_REQUEST & 0xff00
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mov r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff
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orr r3, r3, #OMAP1610_IDLECT1_SLEEP_VAL & 0xff00
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strh r3, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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mov r5, #IDLE_WAIT_CYCLES & 0xff
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orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
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l_1610_2:
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subs r5, r5, #1
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bne l_1610_2
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@ disable instruction cache
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mrc p15, 0, r9, c1, c0, 0
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bic r2, r9, #0x1000
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mcr p15, 0, r2, c1, c0, 0
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nop
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/*
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* Let's wait for the next wake up event to wake us up. r0 can't be
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* used here because r0 holds ARM_IDLECT1
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@@ -301,13 +302,21 @@ l_1610_2:
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* omap1610_cpu_suspend()'s resume point.
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*
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* It will just start executing here, so we'll restore stuff from the
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* stack, reset the ARM_IDLECT1 and ARM_IDLECT2.
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* stack.
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*/
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@ re-enable Icache
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mcr p15, 0, r9, c1, c0, 0
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@ reset the ARM_IDLECT1 and ARM_IDLECT2.
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strh r1, [r4, #ARM_IDLECT2_ASM_OFFSET & 0xff]
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strh r0, [r4, #ARM_IDLECT1_ASM_OFFSET & 0xff]
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@ Restore EMIFF controls
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str r7, [r6, #EMIFF_SDRAM_CONFIG_ASM_OFFSET & 0xff]
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str r8, [r6, #EMIFS_CONFIG_ASM_OFFSET & 0xff]
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@ restore regs and return
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ldmfd sp!, {r0 - r12, pc}
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ldmfd sp!, {r0 - r12, pc}
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ENTRY(omap1610_cpu_suspend_sz)
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.word . - omap1610_cpu_suspend
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